E981.12A39BB ELMOS Semiconductor, E981.12A39BB Datasheet - Page 26

• Manufacturer Part Number: E981.12A39BB
• Description: Interface - Specialized Dual I/O Link Master Transciever
• Manufacturer: ELMOS Semiconductor

Specifications of E981.12A39BB

• Rohs: yes
• Product Type: Dual I/O link Master Transceiver
• Operating Supply Voltage: 3.3 V
• Supply Current: 5.5 mA
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: QFN-44
• Minimum Operating Temperature: - 40 C

Dual IO-Link Master Transceiver with UARTS
ADVANCE PRODUCT INFORMATION - JUL 26, 2011
6.3.6
The IO-Link cycle timer generates the communication cycle. It can be configured in range of 0.4 ms up
to 132.8 ms in register TIM_PER. The cycle time is configured by selecting one range out of three as
shown in Table 15.
T
6.3.6.1
In applications with several channels the device has implemented a cycle synchronization capability.
To enable the cycle snchronization feature set bit SYNC in register TIM CFG to „1“.
Because of independent internal oscillator of several devices in multi port applications the
synchronization has to be repeated after certain period of time. This period of time depends on oscillator
accuracy and application needs. The cycle timer can be configured to run for a number of cycles
determined by bits CNUM[2:0] in register TIM CFG (see Table 16 for details).
If this number of cycles is reached, the bit WAIT4S in register TIM STAT is set and the cycle timer waits
for a resynchronization event from the host controller. Optionally an interrupt can be activated by bit
SYNCIE in register TIM IE to indicate that the device is waiting for an resynchronization event (WAIT4S
in TIM STAT). This interrupt is set after the number of free running cycles is reached under two
conditions:
•
•
The interrupt is cleard by reading TIM STAT.
The synchronization event is generated by the host micro controller using pin SCSN. If pin SCSN is
driven low for T
this low pulse as synchronization event and will start the IO-Link cycle timer for the configured number
of cycles immediately.
This document contains information on a new product. ELMOS Semiconductor AG reserves the right to change specifications and information herein without notice.
ELMOS Semiconductor AG
00b
01b
10b
11b
000b
001b
010b
011b
100b
101b
110b
111b
CYC
the slave response frame is received (number of received characters is equal UART_RXNUM)
idle is detected
PRSC[1:0]
= T
CYC_OFFSET
IO-Link Cycle Timer
Cycle Synchronisation
Table 16: Number of cycles without resynchronization in SYNC mode
IOSYNC
+ T
CNUM[2:0]
CYC_STEP
0.1 ms
0.4 ms
1.6 ms
not used
and no SCK pulse is detected during this period the IO-Link Master IC will interpret
T
TIM_PER[5:0]
CYC_STEP
Table 15: IO-Link cycle time
Data Sheet 26 / 44
N.A.
6.4 ms Offset included
32 ms Offset included
2
4
6
8
10
12
16
32
T
CYC_OFFSET
Number of free running cycles
0.4 ... 6.3 ms
6.4 ... 31.6 ms
32 ... 132.8 ms
QM-No.: 25DS0069E.00
T
CYC
E981.12