E981.12A39BB ELMOS Semiconductor, E981.12A39BB Datasheet

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... TXEN1 TXD1 TXEN2 TXD2 This document contains information on a new product. ELMOS Semiconductor AG reserves the right to change specifications and information herein without notice. ELMOS Semiconductor AG Brief Functional Description This device comes with two independently operating IO-Link MASTER PHYs which make it a perfect fit for 2/4/8/16-port Master applications ...

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... XTAL_OUT D_O 41 XTAL_IN D_I This document contains information on a new product. ELMOS Semiconductor AG reserves the right to change specifications and information herein without notice. ELMOS Semiconductor AG Description Supply current sense input channel 1 Transceiver supply input channel 1 Receiver / general purpose input channel 1 Power ground channel 1 ...

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... Fig. 1: Package Pinout Diagram QFN44L7 Note: Thermal package rating and electrical parameters include soldering the exposed pad to GND. This document contains information on a new product. ELMOS Semiconductor AG reserves the right to change specifications and information herein without notice. ELMOS Semiconductor AG Internally connected. For factory use only. ...

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... MISO RXD1 RXD2 TXEN1 TXD1 TXEN2 TXD2 XTAL_IN XTAL_OUT CLK_REF GND This document contains information on a new product. ELMOS Semiconductor AG reserves the right to change specifications and information herein without notice. ELMOS Semiconductor AG Supply monitor, overtemperature, overvoltage OC[1:2] System Control Gate driver 2x Gate ...

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... ESD protection at pin VDDH ESD protection at pins CQ_OUTx and CQ_INx ESD protection at pin VDDH ESD protection at all other pins This document contains information on a new product. ELMOS Semiconductor AG reserves the right to change specifications and information herein without notice. ELMOS Semiconductor AG Condition continuous t < 500us ...

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... Thermal resistance junction to case Thermal resistance junction to ambient, high conductivity (1) Values are based on multilayer PCB according to JEDEC JESD-51-5. This document contains information on a new product. ELMOS Semiconductor AG reserves the right to change specifications and information herein without notice. ELMOS Semiconductor AG Condition Symbol SIO Mode ...

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... Over current limitation threshold for CQ_OUT=Low Over current limitation threshold for CQ_OUT=High This document contains information on a new product. ELMOS Semiconductor AG reserves the right to change specifications and information herein without notice. ELMOS Semiconductor AG =3.15V to 3.45V, Tamb = -40°C to +105°C, unless otherwise DD = +24V +3.3V and Tamb = +25° ...

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... R (bit FAST=“0“ in CH_CFG) C/Q L/H transition, 10% - 90% This document contains information on a new product. ELMOS Semiconductor AG reserves the right to change specifications and information herein without notice. ELMOS Semiconductor AG =3.15V to 3.45V, Tamb = -40°C to +105°C, unless otherwise DD = +24V +3.3V and Tamb = +25°C. ...

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... UART receiver detects IDLE after N * bit times BIT,IDLE TRX buffer memory size This document contains information on a new product. ELMOS Semiconductor AG reserves the right to change specifications and information herein without notice. ELMOS Semiconductor AG =3.15V to 3.45V, Tamb = -40°C to +105°C, unless otherwise DD = +24V +3.3V and Tamb = +25° ...

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... SCSN and high impedance at MISO MISO data valid time C SCK pulsewidth This document contains information on a new product. ELMOS Semiconductor AG reserves the right to change specifications and information herein without notice. ELMOS Semiconductor AG =3.15V to 3.45V, Tamb = -40°C to +105°C, unless otherwise DD = +24V +3.3V and Tamb = +25° ...

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... SENSE_Lx Pull up resistance at Pins V DR_L1 and DR_L2 in OFF state This document contains information on a new product. ELMOS Semiconductor AG reserves the right to change specifications and information herein without notice. ELMOS Semiconductor AG =3.15V to 3.45V, Tamb = -40°C to +105°C, unless otherwise DD = +24V +3.3V and Tamb = +25°C. ...

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... PMOS Transient response time OFF->ON Transient response time ON->OFF This document contains information on a new product. ELMOS Semiconductor AG reserves the right to change specifications and information herein without notice. ELMOS Semiconductor AG =3.15V to 3.45V, Tamb = -40°C to +105°C, unless otherwise DD = +24V +3.3V and Tamb = +25°C. ...

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... If the VDD supply voltage falls below the V falls below V threshold a power-on-reset is generated. DDPOR This document contains information on a new product. ELMOS Semiconductor AG reserves the right to change specifications and information herein without notice. ELMOS Semiconductor AG threshold this condition is set in the IOLINK threshold the transmitters are disabled ...

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... R R Bit Description L2IE : 1 = Interrupt enable L2 L1IE : 1 = Interrupt enable L1 VDDHIE : 1 = Interrupt enable VDDH VDDIE : 1 = Interrupt enable VDD This document contains information on a new product. ELMOS Semiconductor AG reserves the right to change specifications and information herein without notice. ELMOS Semiconductor AG Description - - L2UV ...

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... The push-pull transmitter is activated with high level on pin TXEN and drives the CQ_OUT pin Low or High in accordance to the inverted logic level on pin TXD. A slope control limits EMC emission. This document contains information on a new product. ELMOS Semiconductor AG reserves the right to change specifications and information herein without notice. ELMOS Semiconductor AG Fig ...

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... The transmitters are switched on after a the over temperature condition disappeared. The over temperature flag is set in CH STAT, to generate an interrupt use bit OTIE in TRX CFG Fig. 5: Transmitter characteristics at overload This document contains information on a new product. ELMOS Semiconductor AG reserves the right to change specifications and information herein without notice. ELMOS Semiconductor AG Fig. 4: Transmitter characteristics Data Sheet E981 ...

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... Fig. 7). d_Off2_OL_confx Fig. 7: Over load while driver was already active This document contains information on a new product. ELMOS Semiconductor AG reserves the right to change specifications and information herein without notice. ELMOS Semiconductor AG Fig. 6: Transmitter over load sequence , followed by the sequence described above using off times Data Sheet E981 ...

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... CH_CFG. If bit SIO is set to „1“ the output control is done by SPI access to register TRX_CFG bits STXD and STXEN. The receiver status can be read by register CH_STAT bit RXD. This document contains information on a new product. ELMOS Semiconductor AG reserves the right to change specifications and information herein without notice. ELMOS Semiconductor AG Data Sheet E981 ...

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... NUME will be set in register TIM_STAT. Optionally an interrupt can be enabled by NUMIE in register TIM IE. The interrupt is cleared by read access to TIM STAT. This document contains information on a new product. ELMOS Semiconductor AG reserves the right to change specifications and information herein without notice. ELMOS Semiconductor AG Fig ...

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... The TRX buffer access is implemented as SPI burst access to reduce the SPI communication overhead (see Chapter SPI Interface). This document contains information on a new product. ELMOS Semiconductor AG reserves the right to change specifications and information herein without notice. ELMOS Semiconductor AG Fig. 10: Host-PHY communication Fig ...

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... UART_TXNUM. For further information about SPI access see chapter SPI Interface. This document contains information on a new product. ELMOS Semiconductor AG reserves the right to change specifications and information herein without notice. ELMOS Semiconductor AG Fig. 12: UART buffer burst read access Data Sheet E981 ...

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... UART is used if bit „SIO“ is not set to „1“ (SIO has priority UART disabled (TXEN, TXD, RXD is used for communication) This document contains information on a new product. ELMOS Semiconductor AG reserves the right to change specifications and information herein without notice. ELMOS Semiconductor AG ...

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... Bit Description IEC-2 : IPD : PDAUTO : 1 = automatic control of Receiver pull down source PDEN : OCIE : OTIE : STXD : STXEN : This document contains information on a new product. ELMOS Semiconductor AG reserves the right to change specifications and information herein without notice. ELMOS Semiconductor PDAUTO PDEN ...

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... Content - NUM6 Reset value 0 0 Access R R/W Bit Description NUM6 .. NUM0: Number of Bytes to be received This document contains information on a new product. ELMOS Semiconductor AG reserves the right to change specifications and information herein without notice. ELMOS Semiconductor AG TDOFF1 TDOFF0 - 0 0 R/W R/W OFF2_OL_CONFx dOFF2_OL_CONF1 ...

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... Framing error (no stop bit), cleared by read access Parity error, cleared by read access Table 14: Receiver status and error register This document contains information on a new product. ELMOS Semiconductor AG reserves the right to change specifications and information herein without notice. ELMOS Semiconductor ...

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... IOSYNC this low pulse as synchronization event and will start the IO-Link cycle timer for the configured number of cycles immediately. This document contains information on a new product. ELMOS Semiconductor AG reserves the right to change specifications and information herein without notice. ELMOS Semiconductor ...

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... Dual IO-Link Master Transceiver with UARTS ADVANCE PRODUCT INFORMATION - JUL 26, 2011 Fig. 13: IO-Link cycle timing with and without synchronisation This document contains information on a new product. ELMOS Semiconductor AG reserves the right to change specifications and information herein without notice. ELMOS Semiconductor AG Data Sheet E981 ...

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... SYNC : 1 = Enable syncronisation Enable timer This document contains information on a new product. ELMOS Semiconductor AG reserves the right to change specifications and information herein without notice. ELMOS Semiconductor AG Description Timer config channel 1 Timer Interrupt enable register channel 1 IO-Link Cycle Timer status register channel 1 ...

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... Cycle timer running, Reception ongoing Cycle timer running, Transmission ongoing Table 20: IO-Link Cycle Timer status register This document contains information on a new product. ELMOS Semiconductor AG reserves the right to change specifications and information herein without notice. ELMOS Semiconductor AG SYNCIE ACCIE 0 ...

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... R/W Bit Description PRSC1 / PRSC0 : Cycle timer prescaler PER5 .. PER0 : Table 21: IO-Link Cycle Timer Period and Prescale configuration This document contains information on a new product. ELMOS Semiconductor AG reserves the right to change specifications and information herein without notice. ELMOS Semiconductor AG PER5 PER4 PER3 ...

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... TXENx and TXDx d_off_wu or the UART. This document contains information on a new product. ELMOS Semiconductor AG reserves the right to change specifications and information herein without notice. ELMOS Semiconductor AG Fig. 14: Wake up procedure Data Sheet E981 ...

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... RDYIE : 1 = Interrupt for RDY (wake up sequence completed) enabled START : 1 = start a wake up signal at channel (always read as '0') Table 23: WURQ configuration and status register This document contains information on a new product. ELMOS Semiconductor AG reserves the right to change specifications and information herein without notice. ELMOS Semiconductor AG WURQ configuration and status register ...

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... The CLK_FAC can be in range of 0x0400 (2048d 0x3FFF (16383d) which allows a wide range of the input frequency recommended to configure the CLK_FAC registers reset condition of the IO- LINK Master IC. This document contains information on a new product. ELMOS Semiconductor AG reserves the right to change specifications and information herein without notice. ELMOS Semiconductor AG CLK ...

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... R/W External access R R Bit Description FAC13 : Clock divider high byte This document contains information on a new product. ELMOS Semiconductor AG reserves the right to change specifications and information herein without notice. ELMOS Semiconductor AG Description Clock status register Clock system control Clock divider register ...

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... PCB. The host has to configure the other master devices accordingly in CLK_CTRL. The CLK_OUT port should be enabled after the IO-Link Master device completely configured to ensure the correct output frequency at system startup. This document contains information on a new product. ELMOS Semiconductor AG reserves the right to change specifications and information herein without notice. ELMOS Semiconductor AG - ...

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... The standard register access is used for all configuration and status registers. An interbyte gap of t has to be ensured by the host. This document contains information on a new product. ELMOS Semiconductor AG reserves the right to change specifications and information herein without notice. ELMOS Semiconductor write access 1 = burst access Fig ...

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... Transmission error is indicated by an interrupt XORIRQ in register ISTAT. This interrupt can not be masked. This document contains information on a new product. ELMOS Semiconductor AG reserves the right to change specifications and information herein without notice. ELMOS Semiconductor AG Fig. 17: UART buffer burst write access Fig ...

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... Dual IO-Link Master Transceiver with UARTS ADVANCE PRODUCT INFORMATION - JUL 26, 2011 6.5.3 SPI Timing This document contains information on a new product. ELMOS Semiconductor AG reserves the right to change specifications and information herein without notice. ELMOS Semiconductor AG Fig. 19: SPI timing Data Sheet E981.12 ...

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... Transmitter interrupt Gate driver interrupt SPI error interrupt Wakeup ready interrupt This document contains information on a new product. ELMOS Semiconductor AG reserves the right to change specifications and information herein without notice. ELMOS Semiconductor AG Fig. 20: IRQ sources and generation Module Transceiver UART and ...

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... TXIRQ1 : 1 = Transmitter 1 IRQ TIRQ2 : 1 = IO-Link cycle timer 2 IRQ TIRQ1 : 1 = IO-Link cycle timer 1 IRQ This document contains information on a new product. ELMOS Semiconductor AG reserves the right to change specifications and information herein without notice. ELMOS Semiconductor AG Description Table 30: Interrupt source register VMIRQ TXIRQ2 ...

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... FET is switched off immidiately. In this mode cyclic switching is disbled. To enable the FET after a shutdown register PDR_STAT has to be read. This document contains information on a new product. ELMOS Semiconductor AG reserves the right to change specifications and information herein without notice. ELMOS Semiconductor AG R ...

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... OC1IRQ : shunt interrupt flag. Cleared after read access. L1ON : 1 = Driver for L1 enabled 0 = Driver for L1 disabled by overcurrent This document contains information on a new product. ELMOS Semiconductor AG reserves the right to change specifications and information herein without notice. ELMOS Semiconductor AG Configuration of PMOS gate control Gate control interrupt enable ...

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... TIM STAT 0x28 TIM PER 0x29 RX STAT 0x2A This document contains information on a new product. ELMOS Semiconductor AG reserves the right to change specifications and information herein without notice. ELMOS Semiconductor AG Reference Page 40 Table 31 Interrupt source register Page 14 Table 5 Voltage monitor status register ...

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... Alexandra Terrace • #09-31 The Comtech • Singapore 118502 © ELMOS Semiconductor AG, 2011. Reproduction, in part or whole, without the prior written consent of ELMOS Semiconductor AG, is prohibited. This document contains information on a new product. ELMOS Semiconductor AG reserves the right to change specifications and information herein without notice. ELMOS Semiconductor AG  ...