E981.12A39BB ELMOS Semiconductor, E981.12A39BB Datasheet - Page 19

• Manufacturer Part Number: E981.12A39BB
• Description: Interface - Specialized Dual I/O Link Master Transciever
• Manufacturer: ELMOS Semiconductor

Specifications of E981.12A39BB

• Rohs: yes
• Product Type: Dual I/O link Master Transceiver
• Operating Supply Voltage: 3.3 V
• Supply Current: 5.5 mA
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: QFN-44
• Minimum Operating Temperature: - 40 C

Dual IO-Link Master Transceiver with UARTS
ADVANCE PRODUCT INFORMATION - JUL 26, 2011
6.3.4
The IO-Link Master IC has two integrated UART interfaces. The UART provides the media access and
bit decoding / encoding and byte framing capabilities as well. UART timing accuracy of 0.1% depends
on the oscillatior configuration described in chapter „Oscillator“.
UART mode is activated by SPI register CH_CFG bit UART. For UART mode the bit „SIO“ has to be
„0“. The UART baudrate has to be configured in register CH_CFG independently for each channel.
The UART byte frame consists of:




Transmission and receive is controlled by the integrated IO-Link cycle timer. For UART communication
the internal cycle timer must be configured and enabled (see chapter „IO-Link cycle timer“).
Each received byte is checked for correct parity and right framing (stop bit). In case of receive errors the
corresponding error flags are set in register RX_STAT and TIM STAT.
The E981.12 provides a 127 byte shared TRX buffer to store transmit and receive frames.
The number of bytes to be transmitted and received must be configured in register UART_TXNUM and
UART_RXNUM. As soon as the configured number of bytes was successfully send and the response
was received bit RDY in register TIM_STAT is set. Optionally an interrupt can be enabled by RDYIE in
register TIM_IE.
If no further UART characters are observed for longer than T
received characters differs from the value in UART_RXNUM (as well as no reception at all was
observed), the error flag NUME will be set in register TIM_STAT. Optionally an interrupt can be enabled
by NUMIE in register TIM IE. The interrupt is cleared by read access to TIM STAT.
This document contains information on a new product. ELMOS Semiconductor AG reserves the right to change specifications and information herein without notice.
ELMOS Semiconductor AG
one start bit (value "0")
eight data bits (LSB first)
an even parity bit and
one stop bit (value "1").
Transceiver UART
Fig. 9: IO-Link frame and cycle timing
Fig. 8: Uart byte frame
Data Sheet 19 / 44
2
, IDLE is detected. If the number of
QM-No.: 25DS0069E.00
E981.12