E981.12A39BB ELMOS Semiconductor, E981.12A39BB Datasheet - Page 20

• Manufacturer Part Number: E981.12A39BB
• Description: Interface - Specialized Dual I/O Link Master Transciever
• Manufacturer: ELMOS Semiconductor

Specifications of E981.12A39BB

• Rohs: yes
• Product Type: Dual I/O link Master Transceiver
• Operating Supply Voltage: 3.3 V
• Supply Current: 5.5 mA
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: QFN-44
• Minimum Operating Temperature: - 40 C

Dual IO-Link Master Transceiver with UARTS
E981.12
ADVANCE PRODUCT INFORMATION - JUL 26, 2011
6.3.4.1
Host - PHY Communication
The timing diagram in Fig. 10 shows the communication between host microcontroller and IO-Link
Master TRX buffer within one cycle when using the internal UARTs. Before writing or reading the
corresponding buffer the UART hast to be enabled.
Fig. 10: Host-PHY communication
After reading the response frame of the current cycle the host has to write the master frame for the next
cycle to be transmitted before the current cycle has been ended. The buffered IO-Link master frame is
sent by E981.12 starting with the next communication cycle (see chapter „IO-Link cycle timer“). The
host microcontroller has to ensure to fill the TRX buffer with the master frame before the next cycle
starts. If the TRX buffer access is not finished till the next cycle start (cycle boundary violation), the
transmission is started delayed.
The TX bytes written to the TRX buffer by SPI are checked by XOR checksum. If the checksum fails
the E981.12 does not transmit data in the next cycle.
The TRX buffer access is implemented as SPI burst access to reduce the SPI communication overhead
(see Chapter SPI Interface).
Fig. 11: UART buffer burst write access
This document contains information on a new product. ELMOS Semiconductor AG reserves the right to change specifications and information herein without notice.
ELMOS Semiconductor AG
Data Sheet 20 / 44
QM-No.: 25DS0069E.00