AT45DB161E-CCUD-T Adesto Technologies, AT45DB161E-CCUD-T Datasheet - Page 35

• Manufacturer Part Number: AT45DB161E-CCUD-T
• Description: Flash 16M 2.5-3.6V 85Mhz Serial Flash
• Manufacturer: Adesto Technologies

Specifications of AT45DB161E-CCUD-T

• Rohs: yes
• Data Bus Width: 8 bit
• Memory Type: Data Flash
• Memory Size: 16 Mbit
• Architecture: Flexible, Uniform Erase
• Timing Type: Synchronous
• Interface Type: SPI
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.5 V
• Maximum Operating Current: 26 mA
• Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: BGA-9
• Factory Pack Quantity: 4000
• Part # Aliases: AT45DB161D-CU

11.
Buffer and Page Size Configuration
The memory array of DataFlash devices is actually larger than other Serial Flash devices in that extra user-accessible
bytes are provided in each page of the memory array. For the AT45DB161E, there are an extra 16 bytes of memory in
each page for a total of an extra 64KB (512-Kbits) of user-accessible memory. Therefore, the device density is actually
16.5-Mbits instead of 16-Mbits.
Some applications, however, may not want to take advantage of this extra memory and instead architect their software to
operate on a “power of 2” binary, logical addressing scheme. To allow this, the DataFlash can be configured so that the
buffer and page sizes are 512 bytes instead of the standard 528 bytes. In addition, the configuration of the buffer and
page sizes is reversible and can be changed from 528 bytes to 512 bytes or from 512 bytes to 528 bytes. The configured
setting is stored in an internal nonvolatile register so that the buffer and page size configuration is not affected by power
cycles. The nonvolatile register has a limit of 10,000 erase/program cycles; therefore, care should be taken to not switch
between the size options more than 10,000 times.
Devices are initially shipped from Adesto with the buffer and page sizes set to 528 bytes. Devices can be ordered from
Adesto pre-configured for the “power of 2” binary size of 512 bytes. For details, see
page
To configure the device for “power of 2” binary page size (512 bytes), a 4-byte opcode sequence of 3Dh, 2Ah, 80h, and
A6h must be clocked into the device. After the last bit of the opcode sequence has been clocked in, the CS pin must be
deasserted to initiate the internally self-timed configuration process and nonvolatile register program cycle. The
programming of the nonvolatile register should take place in a time of t
Status Register will indicate that the device is busy. The device does not need to be power cycled after the completion of
the configuration process and register program cycle in order for the buffer and page size to be configured to 512 bytes.
To configure the device for standard DataFlash page size (528 bytes), a 4-byte opcode sequence of 3Dh, 2Ah, 80h, and
A7h must be clocked into the device. After the last bit of the opcode sequence has been clocked in, the CS pin must be
deasserted to initial the internally self-timed configuration process and nonvolatile register program cycle. The
programming of the nonvolatile register should take place in a time of t
Status Register will indicate that the device is busy. The device does not need to be power cycled after the completion of
the configuration process and register program cycle in order for the buffer and page size to be configured to 528 bytes.
Table 11-1. Buffer and Page Size Configuration Commands
Figure 11-1. Buffer and Page Size Configuration
Command
“Power of 2” binary page size (512 bytes)
DataFlash page size (528 bytes)
CS
SI
63.
Each transition represents eight bits
3Dh
2Ah
80h
Opcode
Byte 4
EP
EP
, during which time the RDY/BUSY bit in the
, during which time the RDY/BUSY bit in the
Adesto AT45DB161E [DATASHEET]
Byte 1
3Dh
3Dh
Section 27., Ordering Information on
Byte 2
2Ah
2Ah
8782D–DFLASH–11/2012
Byte 3
80h
80h
Byte 4
A6h
A7h
35