AT45DB161E-CCUD-T Adesto Technologies, AT45DB161E-CCUD-T Datasheet - Page 12

• Manufacturer Part Number: AT45DB161E-CCUD-T
• Description: Flash 16M 2.5-3.6V 85Mhz Serial Flash
• Manufacturer: Adesto Technologies

Specifications of AT45DB161E-CCUD-T

• Rohs: yes
• Data Bus Width: 8 bit
• Memory Type: Data Flash
• Memory Size: 16 Mbit
• Architecture: Flexible, Uniform Erase
• Timing Type: Synchronous
• Interface Type: SPI
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.5 V
• Maximum Operating Current: 26 mA
• Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: BGA-9
• Factory Pack Quantity: 4000
• Part # Aliases: AT45DB161D-CU

6.6
6.7
buffer is reached, then the device will wrap around back to the beginning of the buffer. When using the binary page size,
the page and buffer address bits correspond to a 21-bit logical address (A20-A0) in the main memory.
After all data bytes have been clocked into the device, a low-to-high transition on the CS pin will start the program
operation in which the device will program the data stored in Buffer 1 into the main memory array. Only the data bytes
that were clocked into the device will be programmed into the main memory.
Example:
The CS pin must be deasserted on a byte boundary (multiples of eight bits); otherwise, the operation will be aborted and
no data will be programmed. The programming of the data bytes is internally self-timed and should take place in a
maximum time of t
programmed). During this time, the RDY/BUSY bit in the Status Register will indicate that the device is busy.
The device also incorporates an intelligent programming algorithm that can detect when a byte location fails to program
properly. If a programming error arises, it will be indicated by the EPE bit in the Status Register.
Page Erase
The Page Erase command can be used to individually erase any page in the main memory array allowing the Buffer to
Main Memory Page Program without Built-In Erase command or the Main Memory Byte/Page Program through Buffer 1
command to be utilized at a later time.
To perform a Page Erase with the standard DataFlash page size (528 bytes), an opcode of 81h must be clocked into the
device followed by three address bytes comprised of two dummy bits, 12 page address bits (PA11 - PA0) that specify the
page in the main memory to be erased, and 10 dummy bits.
To perform a Page Erase with the binary page size (512 bytes), an opcode of 81h must be clocked into the device
followed by three address bytes comprised of three dummy bits, 12 page address bits (A20 - A9) that specify the page in
the main memory to be erased, and nine dummy bits.
When a low-to-high transition occurs on the CS pin, the device will erase the selected page (the erased state is a Logic
1). The erase operation is internally self-timed and should take place in a maximum time of t
RDY/BUSY bit in the Status Register will indicate that the device is busy.
The device also incorporates an intelligent erase algorithm that can detect when a byte location fails to erase properly. If
an erase error arises, it will be indicated by the EPE bit in the Status Register.
Block Erase
The Block Erase command can be used to erase a block of eight pages at one time. This command is useful when
needing to pre-erase larger amounts of memory and is more efficient than issuing eight separate Page Erase
commands.
To perform a Block Erase with the standard DataFlash page size (528 bytes), an opcode of 50h must be clocked into the
device followed by three address bytes comprised of two dummy bits, nine page address bits (PA11 - PA3), and 13
dummy bits. The nine page address bits are used to specify which block of eight pages is to be erased.
To perform a Block Erase with the binary page size (512 bytes), an opcode of 50h must be clocked into the device
followed by three address bytes comprised of three dummy bits, nine page address bits (A20 - A12), and 12 dummy bits.
The nine page address bits are used to specify which block of eight pages is to be erased.
When a low-to-high transition occurs on the CS pin, the device will erase the selected block of eight pages. The erase
operation is internally self-timed and should take place in a maximum time of t
the Status Register will indicate that the device is busy.
The device also incorporates an intelligent erase algorithm that can detect when a byte location fails to erase properly. If
an erase error arises, it will be indicated by the EPE bit in the Status Register.
If only two data bytes were clocked into the device, then only two bytes will be programmed into main
memory and the remaining bytes in the memory page will remain in their previous state.
P
(the program time will be a multiple of the t
BP
time depending on the number of bytes being
Adesto AT45DB161E [DATASHEET]
BE
. During this time, the RDY/BUSY bit in
PE
. During this time, the
8782D–DFLASH–11/2012
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