AT45DB321D-CCU Adesto Technologies, AT45DB321D-CCU Datasheet - Page 7
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AT45DB321D-CCU
Manufacturer Part Number
AT45DB321D-CCU
Description
Flash 32M 2.7-3.6V, 66Mhz Serial Flash
Manufacturer
Adesto Technologies
Datasheet
1.AT45DB321D-CCU.pdf
(51 pages)
Specifications of AT45DB321D-CCU
Rohs
yes
Data Bus Width
8 bit
Memory Type
Data Flash
Memory Size
32 Mbit
Architecture
Flexible, Uniform Erase
Timing Type
Synchronous
Interface Type
SPI
Supply Voltage - Max
3.6 V
Supply Voltage - Min
2.7 V
Maximum Operating Current
15 mA
Operating Temperature
- 40 C to + 85 C
Mounting Style
SMD/SMT
Package / Case
BGA-24
Factory Pack Quantity
378
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT45DB321D-CCU-SL383
Manufacturer:
Adesto Technologies
Quantity:
10 000
5.
5.1
5.2
5.3
5.4
Program and Erase Commands
Buffer Write
Data can be clocked in from the input pin (SI) into either buffer 1 or buffer 2. To load data into the standard DataFlash buffer
(528 bytes), a 1-byte opcode, 84H for buffer 1 or 87H for buffer 2, must be clocked into the device, followed by three address
bytes comprised of 14 don’t care bits and 10 buffer address bits (BFA9 - BFA0). The 10 buffer address bits specify the first byte
in the buffer to be written. To load data into the binary buffers (512 bytes each), a 1-byte 84H opcode for buffer 1 or 87H opcode
for buffer 2 must be clocked into the device, followed by three address bytes comprised of 15 don’t care bits and 9 buffer
address bits (BFA8 - BFA0). The nine buffer address bits specify the first byte in the buffer to be written. After the last address
byte has been clocked into the device, data can then be clocked in on subsequent clock cycles. If the end of the data buffer is
reached, the device will wrap around back to the beginning of the buffer. Data will continue to be loaded into the buffer until a
low-to-high transition is detected on the CS pin.
Buffer to Main Memory Page Program with Built-in Erase
Data written into either buffer 1 or buffer 2 can be programmed into the main memory. A 1-byte opcode, 83H for buffer 1 or 86H
for buffer 2, must be clocked into the device. For the standard DataFlash page size (528 bytes), the opcode must be followed by
three address bytes consist of 1 don’t care bit, 13 page address bits (PA12 - PA0) that specify the page in the main memory to
be written, and 10 don’t care bits. To perform a buffer to main memory page program with built-in erase for the binary page size
(512 bytes), the 83H opcode for buffer 1 or 86H opcode for buffer 2 must be clocked into the device, followed by three address
bytes consisting of 2 don’t care bits, 13 page address bits (A21 - A9) that specify the page in the main memory to be written, and
9 don’t care bits. When a low-to-high transition occurs on the CS pin, the part will first erase the selected page in main memory
(the erased state is a logic one) and then program the data stored in the buffer into the specified page in main memory. The
erase and the programming of the page are internally self-timed, and should take place in a maximum time of t
time, the status register and the RDY/BUSY pin will indicate that the part is busy.
Buffer to Main Memory Page Program without Built-in Erase
A previously-erased page within main memory can be programmed with the contents of either buffer 1 or buffer 2. A one-byte
opcode, 88H for buffer 1 or 89H for buffer 2, must be clocked into the device. For the standard DataFlash page size (528 bytes),
the opcode must be followed by three address bytes that consist of 1 don’t care bit, 13 page address bits (PA12 - PA0) that
specify the page in the main memory to be written, and 10 don’t care bits. To perform a buffer to main memory page program
without built-in erase for the binary page size (512 bytes), the 88H opcode for buffer 1 or 89H opcode for buffer 2 must be
clocked into the device, followed by three address bytes consisting of 2 don’t care bits, 13 page address bits (A21 - A9) that
specify the page in the main memory to be written, and 9 don’t care bits. When a low-to-high transition occurs on the CS pin, the
part will program the data stored in the buffer into the specified page in the main memory. It is necessary that the page in main
memory being programmed has been previously erased using one of the erase commands (page erase or block erase). The
programming of the page is internally self-timed, and should take place in a maximum time of t
register and the RDY/BUSY pin will indicate that the part is busy.
Page Erase
The page erase command can be used to individually erase any page in the main memory array, allowing the buffer to main
memory page program to be utilized at a later time. To perform a page erase in the standard DataFlash page size (528 bytes),
an opcode of 81H must be loaded into the device, followed by three address bytes comprised of 1 don’t care bit, 13 page
address bits (PA12 - PA0) that specify the page in the main memory to be erased, and 10 don’t care bits. To perform a page
erase in the binary page size (512 bytes), the 81H opcode must be loaded into the device, followed by three address bytes
consisting of 2 don’t care bits, 13 page address bits (A21 - A9) that specify the page in the main memory to be erased, and 9
don’t care bits. When a low-to-high transition occurs on the CS pin, the part will erase the selected page (the erased state is a
logical 1). The erase operation is internally self-timed, and should take place in a maximum time of t
status register and the RDY/BUSY pin will indicate that the part is busy.
AT45DB321D [DATASHEET]
P
. During this time, the status
PE
3597R–DFLASH–11/2012
. During this time, the
EP
. During this
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