AT45DB321D-CCU Adesto Technologies, AT45DB321D-CCU Datasheet - Page 33

• Manufacturer Part Number: AT45DB321D-CCU
• Description: Flash 32M 2.7-3.6V, 66Mhz Serial Flash
• Manufacturer: Adesto Technologies

Specifications of AT45DB321D-CCU

• Rohs: yes
• Data Bus Width: 8 bit
• Memory Type: Data Flash
• Memory Size: 32 Mbit
• Architecture: Flexible, Uniform Erase
• Timing Type: Synchronous
• Interface Type: SPI
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V
• Maximum Operating Current: 15 mA
• Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: BGA-24
• Factory Pack Quantity: 378

19.1
Utilizing the RapidS Function
To take advantage of the RapidS function's ability to operate at higher clock frequencies, a full clock cycle must be used to
transmit data back and forth across the serial bus. The DataFlash device is designed to always clock its data out on the falling
edge of the SCK signal and clock data in on the rising edge of SCK.
For full clock cycle operation to be achieved when the DataFlash device is clocking data out on the falling edge of SCK, the host
controller should wait until the next falling edge of SCK to latch the data in. Similarly, the host controller should clock its data out
on the rising edge of SCK in order to give the DataFlash device a full clock cycle to latch the incoming data in on the next rising
edge of SCK.
Figure 19-1. RapidS Mode
Figure 19-2. Reset Timing
Note:
Slave
MOSI = Master Out, Slave In
MISO = Master In, Slave Out
The Master is the host controller and the Slave is the DataFlash
The Master always clocks data out on the rising edge of SCK and always clocks data in on the falling edge of SCK.
The Slave always clocks data out on the falling edge of SCK and always clocks data in on the rising edge of SCK.
SO (OUTPUT)
A.
B.
C. Master clocks out second bit of BYTE-MOSI on the same rising edge of SCK
D. Last bit of BYTE-MOSI is clocked out from the Master
E.
F.
G. Master clocks in first bit of BYTE-SO
H. Slave clocks out second bit of BYTE-SO
I.
SI (INPUT)
MOSI
MISO
SCK
Master clocks out first bit of BYTE-MOSI on the rising edge of SCK
Slave clocks in first bit of BYTE-MOSI on the next rising edge of SCK
Last bit of BYTE-MOSI is clocked into the slave
Slave clocks out first bit of BYTE-SO
Master clocks in last bit of BYTE-SO
RESET
CS
SCK
CS
The CS signal should be in the high state before the RESET signal is deasserted.
A
1
B
MSB
C
2
High impedance
3
4
BYTE-MOSI
5
6
7
D
8
E
LSB
F
1
G
MSB
2
H
3
t RST
AT45DB321D [DATASHEET]
t REC
4
BYTE-SO
High impedance
5
6
3597R–DFLASH–11/2012
t CSS
7
8
I
LSB
1
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