S25FL128SDPMFIG11 Spansion, S25FL128SDPMFIG11 Datasheet - Page 91
![no-image](/images/no-image-200.jpg)
S25FL128SDPMFIG11
Manufacturer Part Number
S25FL128SDPMFIG11
Description
Flash 128Mb 3V 66MHz Serial NOR Flash
Manufacturer
Spansion
Datasheet
1.S25FL128SAGNFI001.pdf
(153 pages)
Specifications of S25FL128SDPMFIG11
Rohs
yes
Data Bus Width
1 bit
Memory Type
Flash
Memory Size
128 Mbit
Architecture
Uniform
Timing Type
Asynchronous
Interface Type
SPI
Supply Voltage - Max
3.6 V
Supply Voltage - Min
2.7 V
Maximum Operating Current
100 mA
Operating Temperature
- 40 C to + 85 C
Mounting Style
SMD/SMT
Package / Case
SO-16
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July 12, 2012 S25FL128S_256S_00_05
10.3.15
10.3.16
CS S #
SCK
SO
SI
Write VDLR (WVDLR 4Ah)
Data Learning Pattern Read (DLPRD 41h)
Before the Write VDLR (WVDLR) command can be accepted by the device, a Write Enable (WREN)
command must be issued and decoded by the device. After the Write Enable (WREN) command has been
decoded successfully, the device will set the Write Enable Latch (WEL) to enable WVDLR operation.
The WVDLR command is entered by shifting the instruction and the data byte on SI.
CS# must be driven to the logic high state after the eighth (8th) bit of data has been latched. If not, the
WVDLR command is not executed. As soon as CS# is driven to the logic high state, the WVDLR operation is
initiated with no delays. The maximum clock frequency for the PNVDLR command is 133 MHz.
The instruction is shifted on SI, then the 8-bit DLP is shifted out on SO. It is possible to read the DLP
continuously by providing multiples of eight clock cycles. The maximum operating clock frequency for the
DLPRD command is 133 MHz.
MSB
7
0
SCK
CS S #
SO
SI
6
1
5
2
High Impedance
4
I I nstruction
Figure 10.21 DLP Read (DLPRD) Command Sequence
3
3
4
2
MSB
Figure 10.20 Write VDLR (WVDLR) Command Sequence
7
5
D a t a
0
1
6
6
1
0
S25FL128S and S25FL256S
7
5
MSB
S h e e t
2
7
High Impedance
8
4
I I nstruction
3
6
9
3
Data Learning Pattern
4
5
10
2
4
5
11
1
3
6
12
0
2
13
7
MSB
7
1
14
8
6
0
15
9
Data Learning Pattern
MSB
5
7
10
16
6
4
17
11
Data Learning Pattern
5
3
18
12
4
2
19
13
3
20
1
14
2
21
0
15
1
22
0
23
91
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