S25FL128SDPMFIG11 Spansion, S25FL128SDPMFIG11 Datasheet - Page 31

• Manufacturer Part Number: S25FL128SDPMFIG11
• Description: Flash 128Mb 3V 66MHz Serial NOR Flash
• Manufacturer: Spansion

Specifications of S25FL128SDPMFIG11

• Rohs: yes
• Data Bus Width: 1 bit
• Memory Type: Flash
• Memory Size: 128 Mbit
• Architecture: Uniform
• Timing Type: Asynchronous
• Interface Type: SPI
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V
• Maximum Operating Current: 100 mA
• Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SO-16

July 12, 2012 S25FL128S_256S_00_05
4.3.19
4.3.20
4.3.21
4.3.22
4.3.23
4.3.24
DDR Dual Input Cycle - Host to Memory Transfer
DDR Quad Input Cycle - Host to Memory Transfer
DDR Latency Cycle
DDR Single Output Cycle - Memory to Host Transfer
DDR Dual Output Cycle - Memory to Host Transfer
DDR Quad Output Cycle - Memory to Host Transfer
The DDR Dual I/O Read command sends address, and mode bits to the memory only on the IO0 and IO1
signals. Two bits are transferred on the rising edge of SCK and two bits on the falling edge in each cycle. The
host keeps RESET# high, and CS# low. The IO2 and IO3 signals are ignored by the memory.
The next interface state following the delivery of address and mode bits is a DDR Latency Cycle.
The DDR Quad I/O Read command sends address, and mode bits to the memory on all the IO signals. Four
bits are transferred on the rising edge of SCK and four bits on the falling edge in each cycle. The host keeps
RESET# high, and CS# low.
The next interface state following the delivery of address and mode bits is a DDR Latency Cycle.
DDR Read commands may have one to several latency cycles during which read data is read from the main
flash memory array before transfer to the host. The number of latency cycles are determined by the Latency
Code in the configuration register (CR[7:6]). During the latency cycles, the host keeps RESET# high and CS#
low. The host may not drive the IO signals during these cycles. So that there is sufficient time for the host
drivers to turn off before the memory begins to drive. This prevents driver conflict between host and memory
when the signal direction changes. The memory has an option to drive all the IO signals with a Data Learning
Pattern (DLP) during the last 4 latency cycles. The DLP option should not be enabled when there are fewer
than five latency cycles so that there is at least one cycle of high impedance for turn around of the IO signals
before the memory begins driving the DLP. When there are more than 4 cycles of latency the memory does
not drive the IO signals until the last four cycles of latency.
The next interface state following the last latency cycle is a DDR Single, Dual, or Quad Output Cycle,
depending on the instruction.
The DDR Fast Read command returns bits to the host only on the SO / IO1 signal. One bit is transferred on
the rising edge of SCK and one bit on the falling edge in each cycle. The host keeps RESET# high, and CS#
low. The other IO signals are not driven by the memory.
The next interface state continues to be DDR Single Output Cycle until the host returns CS# to high ending
the command.
The DDR Dual I/O Read command returns bits to the host only on the IO0 and IO1 signals. Two bits are
transferred on the rising edge of SCK and two bits on the falling edge in each cycle. The host keeps RESET#
high, and CS# low. The IO2 and IO3 signals are not driven by the memory.
The next interface state continues to be DDR Dual Output Cycle until the host returns CS# to high ending the
command.
The DDR Quad I/O Read command returns bits to the host on all the IO signals. Four bits are transferred on
the rising edge of SCK and four bits on the falling edge in each cycle. The host keeps RESET# high, and CS#
low.
The next interface state continues to be DDR Quad Output Cycle until the host returns CS# to high ending the
command.
D a t a
S25FL128S and S25FL256S
S h e e t
31