S25FL128SDPMFIG11 Spansion, S25FL128SDPMFIG11 Datasheet - Page 103

• Manufacturer Part Number: S25FL128SDPMFIG11
• Description: Flash 128Mb 3V 66MHz Serial NOR Flash
• Manufacturer: Spansion

Specifications of S25FL128SDPMFIG11

• Rohs: yes
• Data Bus Width: 1 bit
• Memory Type: Flash
• Memory Size: 128 Mbit
• Architecture: Uniform
• Timing Type: Asynchronous
• Interface Type: SPI
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V
• Maximum Operating Current: 100 mA
• Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SO-16

July 12, 2012 S25FL128S_256S_00_05
SCLK
SCLK
CS#
CS#
IO0
IO1
IO0
IO1
7
0
23
24 Bit Address
Figure 10.41 DDR Fast Read Initial Access (3-byte Address, 0Dh [ExtAdd=0, EHPLC=11b])
0
Figure 10.41 on page 103
bit SDR instruction sequence to reduce initial access time (improves XIP performance). The Mode bits control
the length of the next DDR Fast Read operation through the inclusion or exclusion of the first byte instruction
code. If the upper nibble (IO[7:4]) and lower nibble (IO[3:0]) of the Mode bits are complementary (i.e. 5h and
Ah) then the next address can be entered (after CS# is raised high and then asserted low) without requiring
the 0Dh or 0Eh instruction, as shown in
command sequence. The following sequences will release the device from this continuous DDR Fast Read
mode; after which, the device can accept standard SPI commands:
CS# should not be driven high during mode or dummy bits as this may make the mode bits indeterminate.
The HOLD function is not valid during any part of a Fast DDR Command.
Although the data learning pattern (DLP) is programmable, the following example shows example of the DLP
of 34h. The DLP 34h (or 00110100) will be driven on each of the active outputs (i.e. all four IOs on a x4
device, both IOs on a x2 device and the single SO output on a x1 device). This pattern was chosen to cover
both DC and AC data transition scenarios. The two DC transition scenarios include data low for a long period
of time (two half clocks) followed by a high going transition (001) and the complementary low going transition
(110). The two AC transition scenarios include data low for a short period of time (one half clock) followed by
a high going transition (101) and the complementary low going transition (010). The DC transitions will
typically occur with a starting point closer to the supply rail than the AC transitions that may not have fully
settled to their steady state (DC) levels. In many cases the DC transitions will bound the beginning of the data
valid period and the AC transitions will bound the ending of the data valid period. These transitions will allow
the host controller to identify the beginning and ending of the valid data eye. Once the data eye has been
characterized the optimal data capture point can be chosen. See
Registers on page 65
1
6
12 cycles
22
1. During the DDR Fast Read Command Sequence, if the Mode bits are not complementary the next
2. During any operation, if CS# toggles high to low to high for eight cycles (or less) and data input (SI)
2
5
1
time CS# is raised high the device will be released from the continuous DDR Fast Read mode.
are not set for a valid instruction sequence, then the device will be released from DDR Fast Read
mode.
12
0
Instruction
3
4
8 cycles
Figure 10.42 Continuous DDR Fast Read Subsequent Access
7
4
3
13
6
for more details.
5
2
(3-byte Address [ExtAdd=0, EHPLC=11b])
5
D a t a
14
and
4 cycles
6
1
4
Mode
Figure 10.43 on page
S25FL128S and S25FL256S
3
7
0
15
S h e e t
24 Bit Address
2
2
Figure 10.42
8
12 cycles
2
1
1
16
19
0
0
7
20
Dummy
1 cyc
6
and
17
104. This added feature removes the need for the eight
5
21
4 cycles
Figure
Mode
4
7
3
22
18
2
10.44, thus, eliminating eight cycles from the
6
Section 8.5.11, SPI DDR Data Learning
1
23
0
5
Dummy
8
1 cyc
24
per data
4 cycles
4
7
25
3
19
6
2
5
26
4 cycles
per data
4
1
3
20
27
2
0
1
28
7
0
21
7
29
6
6
103