S25FL128SDPMFIG11 Spansion, S25FL128SDPMFIG11 Datasheet - Page 23

• Manufacturer Part Number: S25FL128SDPMFIG11
• Description: Flash 128Mb 3V 66MHz Serial NOR Flash
• Manufacturer: Spansion

Specifications of S25FL128SDPMFIG11

• Rohs: yes
• Data Bus Width: 1 bit
• Memory Type: Flash
• Memory Size: 128 Mbit
• Architecture: Uniform
• Timing Type: Asynchronous
• Interface Type: SPI
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V
• Maximum Operating Current: 100 mA
• Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SO-16

July 12, 2012 S25FL128S_256S_00_05
 The address or mode bits may be followed by write data to be stored in the memory device or by a read
 Write data bit transfers occur on SCK rising edge, in SDR commands, or on every SCK edge, in DDR
 SCK continues to toggle during any read access latency period. The latency may be zero to several SCK
 If the command returns read data to the host, the device continues sending data transfers until the host
 At the end of a command that does not return data, the host drives the CS# input high. The CS# signal
 All instruction, address, and mode bits are shifted into the device with the Most Significant Bits (MSB) first.
 All attempts to read the flash memory array during a program, erase, or a write cycle (embedded
 Depending on the command, the time for execution varies. A command to read status information from an
latency period before read data is returned to the host.
commands.
cycles (also referred to as dummy cycles). At the end of the read latency cycles, the first read data bits are
driven from the outputs on SCK falling edge at the end of the last read latency cycle. The first read data
bits are considered transferred to the host on the following SCK rising edge. Each following transfer occurs
on the next SCK rising edge, in SDR commands, or on every SCK edge, in DDR commands.
takes the CS# signal high. The CS# signal can be driven high after any transfer in the read data sequence.
This will terminate the command.
must go high after the eighth bit, of a stand alone instruction or, of the last write data byte that is
transferred. That is, the CS# signal must be driven high when the number of clock cycles after CS# signal
was driven low is an exact multiple of eight cycles. If the CS# signal does not go high exactly at the eight
SCK cycle boundary of the instruction or write data, the command is rejected and not executed.
The data bits are shifted in and out of the device MSB first. All data is transferred in byte units with the
lowest address byte sent first. Following bytes of data are sent in lowest to highest byte address order i.e.
the byte address increments.
operations) are ignored. The embedded operation will continue to execute without any affect. A very
limited set of commands are accepted during an embedded operation. These are discussed in the
individual command descriptions.
executing command is available to determine when the command completes execution and whether the
command was successful.
D a t a
S25FL128S and S25FL256S
S h e e t
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