iCE65L04F-LCB284I Lattice, iCE65L04F-LCB284I Datasheet - Page 84

• Manufacturer Part Number: iCE65L04F-LCB284I
• Description: FPGA - Field Programmable Gate Array iCE65 3520 LUTs, 1.0 1.2V Ultra Low-Power
• Manufacturer: Lattice

Specifications of iCE65L04F-LCB284I

• Rohs: yes
• Number Of Gates: 3520
• Number Of Logic Blocks: 20
• Number Of I/os: 176
• Maximum Operating Frequency: 256 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: CBGA-284
• Distributed Ram: 80 Kbit
• Minimum Operating Temperature: - 40 C
• Operating Supply Current: 26 uA
• Factory Pack Quantity: 168

iCE65 Ultra Low-Power mobileFPGA
(2.42, 30-MAR-2012)
84
Die Cross Reference
The tables in this section list all the pads on a specific die type and provide a cross reference on how a specific pad
connects to a ball or pin in each of the available package offerings. Similarly, the tables provide the pad coordinates
for the die-based version of the product (DiePlus). These tables also provide a way to prototype with one package
option and then later move to a different package or die.
As described in
Similarly, as described in
output. PIO pairs in I/O Bank 3 are optionally differential inputs or differential outputs. PIO pairs in all other I/O
Banks are optionally differential outputs. In the tables, differential pairs are surrounded by a heavy blue box.
iCE65L04
Table 45
package styles. Most VCC, VCCIO, and GND pads are double-bonded inside the package although the table shows
only a single connection.
For additional information on the iCE65L04 DiePlus product, please refer to the following data sheet.
PIO3_00/DP00A
PIO3_01/DP00B
PIO3_02/DP01A
PIO3_03/DP01B
PIO3_04/DP02A
PIO3_05/DP02B
PIO3_06/DP03A
PIO3_07/DP03B
PIO3_08/DP04A
PIO3_09/DP04B
PIO3_10/DP05A
PIO3_11/DP05B
PIO3_12/DP06A
PIO3_13/DP06B
PIO3_14/DP07A
PIO3_15/DP07B
PIO3_16/DP08A
PIO3_17/DP08B
DiePlus Advantage FPGA Known Good Die
lists all the pads on the iCE65L04 die and how these pads connect to the balls or pins in the supported
Pad Name
iCE65L04
VCCIO_3
VCCIO_3
VCCIO_3
GND
GND
GND
GND
GND
VCC
VCC
“Input and Output Register Control per PIO
“Differential Inputs and
VQ100
Table 45: iCE65L04 Die Cross Reference
10
11
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1
2
3
4
5
6
7
8
9
CB132
DiePlus
D3
D4
D1
H6
G6
B1
C1
C3
F1
E3
E4
E1
F4
F3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Outputs” on page 12, a PIO pair can form a differential input or
™
CB196
Family
C1
B1
D3
C3
D1
D2
H9
D4
A9
A9
K1
G6
F1
E3
E1
E2
E4
F3
F4
F5
E5
—
—
—
—
—
—
—
Pair” on page 16, PIO pairs share register control inputs.
CB284
M10
L10
H7
H8
H5
D3
H3
H1
G5
G7
K5
K8
K7
E3
G3
K3
K1
F5
F3
L1
—
J7
—
J8
J5
J3
—
J1
Pad
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
1
2
3
4
5
6
7
8
9
Lattice Semiconductor Corporation
X (µm)
129.40
231.40
129.40
231.40
129.40
231.40
129.40
231.40
129.40
231.40
129.40
231.40
129.40
231.40
129.40
231.40
129.40
231.40
129.40
231.40
129.40
231.40
129.40
231.40
129.40
231.40
129.40
231.40
www.latticesemi.com
2,687.75
2,642.74
2,597.75
2,552.74
2,507.75
2,462.74
2,417.75
2,372.74
2,327.75
2,292.74
2,257.75
2,222.74
2,187.75
2,152.74
2,117.75
2,082.74
2,047.75
2,012.74
1,977.75
1,942.74
1,907.75
1,872.74
1,837.75
1,802.74
1,767.75
1,732.74
1,697.75
1,662.74
Y (µm)