iCE65L04F-LCB284I Lattice, iCE65L04F-LCB284I Datasheet - Page 23

• Manufacturer Part Number: iCE65L04F-LCB284I
• Description: FPGA - Field Programmable Gate Array iCE65 3520 LUTs, 1.0 1.2V Ultra Low-Power
• Manufacturer: Lattice

Specifications of iCE65L04F-LCB284I

• Rohs: yes
• Number Of Gates: 3520
• Number Of Logic Blocks: 20
• Number Of I/os: 176
• Maximum Operating Frequency: 256 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: CBGA-284
• Distributed Ram: 80 Kbit
• Minimum Operating Temperature: - 40 C
• Operating Supply Current: 26 uA
• Factory Pack Quantity: 168

Lattice Semiconductor Corporation
www.latticesemi.com
Read Operations
When the WCLKE signal is Low, the clock to the RAM4K block is disabled, keeping the RAM in its lowest power
mode.
To write data into the RAM4K block, perform the following operations.
Figure 19
RAM4K block. By default, all RAM4K read operations are synchronized to the rising edge of RCLK although the
clock is invertible as shown in
Disabled
Disabled
Disabled
Write
Data
Masked
Write
Operation






shows the logic involved in reading a location from RAM.
Supply a valid address on the WADDR[7:0] address input port
Supply valid data on the WDATA[15:0] data input port
To write or mask selected data bits, set the associated MASK input port accordingly. For example, write
operations on data bit D[i] are controlled by the associated MASK[i] input.
Enable the RAM4K write port (WE = 1)
Enable the RAM4K write clock (WCLKE = 1)
Apply a rising clock edge on WCLK (assuming that the clock is not inverted)


MASK[i] = 0: Write operations are enabled for data line WDATA[i]
MASK[i] = 1: Mask write operations are disabled for data line WDATA[i]
WDATA[15:0]
WDATA[i]
Data
X
X
X
WADDR[7:0]
WDATA[BIT]
MASK[BIT]
Figure
WCLKE
MASK[15:0]
WCLK
MASK[i] = 0
MASK[i] = 1
Table 18: RAM4K Write Operations
Mask Bit
Figure 18: RAM4K Bit Write Logic
WE
19.
X
X
WADDR[7:0]
Address
WADDR
WADDR
X
X
RAM[LOCATION][BIT]
Enable
Write
Table 19
WE
X
0
1
1
D
EN
describes various read operations for a
WCLKE
Enable
Clock
X
X
0
1
1
WCLK
Clock
X
X
0
↑
↑
(2.42, 30-MAR-2011)
RAM[WADDR][i]
RAM[WADDR][i]
RAM Location
= No change
= WDATA[i]
No change
No change
No change
23