iCE65L04F-LCB284I Lattice, iCE65L04F-LCB284I Datasheet - Page 35

• Manufacturer Part Number: iCE65L04F-LCB284I
• Description: FPGA - Field Programmable Gate Array iCE65 3520 LUTs, 1.0 1.2V Ultra Low-Power
• Manufacturer: Lattice

Specifications of iCE65L04F-LCB284I

• Rohs: yes
• Number Of Gates: 3520
• Number Of Logic Blocks: 20
• Number Of I/os: 176
• Maximum Operating Frequency: 256 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: CBGA-284
• Distributed Ram: 80 Kbit
• Minimum Operating Temperature: - 40 C
• Operating Supply Current: 26 uA
• Factory Pack Quantity: 168

Lattice Semiconductor Corporation
www.latticesemi.com
The SPI control signals are defined in
After configuration, the SPI port pins are available to the user-application as additional PIO pins, supplied by the
SPI_VCC input voltage, essentially providing a fifth “mini” I/O bank.
Enabling SPI Configuration Interface
The optional 10 kΩ pull-down resistor on the SPI_SS_B signal ensures that the iCE65 FPGA powers up in the SPI
peripheral mode. Optionally, the application processor drives the SPI_SS_B pin Low when CRESET_B is released,
forcing the iCE65 FPGA into SPI peripheral mode.
SPI Peripheral Configuration Process
Figure 29
configuration process. The actual timing specifications appear in
by driving the iCE65 CRESET_B pin Low, resetting the iCE65 FPGA. Similarly, the AP holds the iCE65’s SPI_SS_B
pin Low. The AP must hold the CRESET_B pin Low for at least 200 ns. Ultimately, the AP either releases the
CRESET_B pin and allows it to float High via the 10 kΩ pull-up resistor to VCCIO_2 or drives CRESET_B High. The
iCE65 FPGA enters SPI peripheral mode when the CRESET_B pin returns High while the SPI_SS_B pin is Low.
Table 29:
CDONE
CRESET_B
SPI_VCC
SPI_SI
SPI_SO
SPI_SS_B
SPI_SCK
Signal
Name
illustrates the interface timing for the SPI peripheral mode and
SPI Peripheral Configuration Interface Pins (SPI_SS_B Low when CRESET_B Released)
AP_VCCIO
AP  iCE65
AP  iCE65
AP  iCE65
AP  iCE65
AP  iCE65
AP  iCE65
Direction
Supply
Figure 28:
iCE65 I/O
VCCIO_2
SPI_VCC
Application
Supply
Processor
iCE65 SPI Peripheral Configuration Interface
Table
25.
Configuration Done output from iCE65. Connect to a 10kΩ pull-up
resistor to the application processor I/O voltage, AP_VCC.
Configuration Reset input on iCE65. Typically driven by AP using an
open-drain driver, which also requires a 10kΩ pull-up resistor to
VCCIO_2.
SPI Flash PROM voltage supply input.
SPI Serial Input to the iCE65 FPGA, driven by the application processor.
SPI Serial Output from CE65 device to the application processor. Not
actually used during SPI peripheral mode configuration but required if
the SPI interface is also used to program the NVCM.
SPI Slave Select output from the application processor. Active Low.
Optionally hold Low prior to configuration using a 10kΩ pull-down
resistor to ground.
SPI Slave Clock output from the application processor.
10 kΩ
AP_VCCIO
VCCIO_2
10 kΩ
10 kΩ
CRESET_B
SPI_SS_B
SPI_SCK
SPI_SO
CDONE
SPI_SI
Table
(I/O Bank 2)
(SPI Bank)
60. The application processor (AP) begins
Description
iCE65
iCE65
Figure 30
VCCIO_2
SPI_VCC
(2.42, 30-MAR-2011)
outlines the resulting
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