iCE65L04F-LCB284I Lattice, iCE65L04F-LCB284I Datasheet - Page 12

• Manufacturer Part Number: iCE65L04F-LCB284I
• Description: FPGA - Field Programmable Gate Array iCE65 3520 LUTs, 1.0 1.2V Ultra Low-Power
• Manufacturer: Lattice

Specifications of iCE65L04F-LCB284I

• Rohs: yes
• Number Of Gates: 3520
• Number Of Logic Blocks: 20
• Number Of I/os: 176
• Maximum Operating Frequency: 256 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: CBGA-284
• Distributed Ram: 80 Kbit
• Minimum Operating Temperature: - 40 C
• Operating Supply Current: 26 uA
• Factory Pack Quantity: 168

iCE65 Ultra Low-Power mobileFPGA
(2.42, 30-MAR-2012)
12
Differential Inputs and Outputs
Table 8
Programmable Output Drive Strength
Each PIO in I/O Bank 3 offers programmable output drive strength, as listed in
MDDR I/O standards, the output driver has settings for static drive currents ranging from 2 mA to 16 mA output
drive current, depending on the I/O standard and supply voltage.
The SSTL18 and SSTL2 I/O standards offer full- and half-strength drive current options
All PIO pins support “single-ended” I/O standards, such as LVCMOS. However, iCE65 FPGAs also support
differential I/O standards where a single data value is represented by two complementary signals transmitted or
received using a pair of PIO pins. The PIO pins in I/O Bank 3 of iCE65L04 and iCE65L08L08 support Low-Voltage
Differential Swing (LVDS) and SubLVDS inputs as shown in
I/O banks.
Differential Inputs Only on I/O Bank 3 of iCE65L04 and iCE65L08
Differential receivers are required for popular applications such as LVDS and LVPECL clock inputs, camera
interfaces, and for various telecommunications standards.
Specific pairs of PIO pins in I/O Bank 3 form a differential input. Each pair consists of a DPxxA and DPxxB pin,
where “xx” represents the pair
the complement of the signal. Typically, the resulting signal pair is routed on the printed circuit board (PCB) with
matched 50Ω signal impedance. The differential signaling, the low voltage swing, and the matched signal routing
are ideal for communicating very-high frequency signals. Differential signals are generally also more tolerant of
system noise and generate little EMI themselves.
The LVDS input circuitry requires 2.5V on the VCCIO_3 voltage supply. Similarly, the SubLVDS input circuitry
requires 1.8V on the VCCIO_3 voltage supply. For electrical specifications, see
Each differential input pair requires an external 100 Ω termination resistor, as shown in
The PIO pins that make up a differential input pair are indicated with a blue bounding box in the footprint diagrams
and in the pinout tables.
VCCIO_3 Voltage
Compatible I/O
Standards
lists the I/O standards that can co-exist in I/O Bank 3, depending on the VCCIO_3 voltage.
Table 8:
Compatible I/O Standards in I/O Bank 3 of iCE65L04 and iCE65L08
SB_LVCMOS33_8
number.
3.3V
The DPxxB receives the true version of the signal while the DPxxA receives
Any SB_LVCMOS25
SB_SSTL2_Class_2
SB_SSTL2_Class_1
SB_LVDS_INPUT
™
Family
2.5V
Figure
8. Differential outputs are available in all four
Any SB_LVCMOS18
SB_SSTL18_HALF
SB_SSTL18_FULL
SB_LVDS_INPUT
SB_MDDR10
SB_MDDR8
SB_MDDR4
SB_MDDR2
Lattice Semiconductor Corporation
“Differential
1.8V
Table
Figure
8. For the LVCMOS and
Inputs” on page 100.
8.
www.latticesemi.com
Any SB_LVCMOS15
1.5V