iCE65L04F-LCB284I Lattice, iCE65L04F-LCB284I Datasheet - Page 73

• Manufacturer Part Number: iCE65L04F-LCB284I
• Description: FPGA - Field Programmable Gate Array iCE65 3520 LUTs, 1.0 1.2V Ultra Low-Power
• Manufacturer: Lattice

Specifications of iCE65L04F-LCB284I

• Rohs: yes
• Number Of Gates: 3520
• Number Of Logic Blocks: 20
• Number Of I/os: 176
• Maximum Operating Frequency: 256 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: CBGA-284
• Distributed Ram: 80 Kbit
• Minimum Operating Temperature: - 40 C
• Operating Supply Current: 26 uA
• Factory Pack Quantity: 168

Lattice Semiconductor Corporation
www.latticesemi.com
Pinout Differences between iCE65L04 and iCE65L08 in CB196 Package
Table 43
package. The table also describes the functional differences between these pins, which is critical when designing a
CB196 footprint that supports both the iCE65L04 and the iCE65L08 devices. In some cases, only the differential
inputs are swapped; single-ended I/Os are not affected. A swapped differential pair can be inverted internally for
functional equivalence. In other cases, a global buffer input is swapped with another PIO pin in the same bank.
Ball Number
lists the package balls that are different between the pinouts for iCE65L04 and the iCE65L08 in the CB196
M7
G1
G2
H3
H4
K3
K4
N8
E1
E2
F3
F4
L7
P5
Table 43:
Pinout Differences between iCE65L04 and iCE65L08 in CB196 Package
GBIN7/PIO3/DP07B
PIO3/DP03A
PIO3/DP05A
PIO3/DP07A
PIO3/DP11A
PIO3/DP16A
PIO3/DP03B
PIO3/DP05B
PIO3/DP11B
PIO3/DP16B
GBIN4/PIO2
GBIN5/PIO2
iCE65L04
PIO2
PIO2
GBIN7/PIO3/DP07B
PIO3/DP03B
PIO3/DP03A
PIO3/DP05B
PIO3/DP05A
PIO3/DP11A
PIO3/DP11B
PIO3/DP07A
PIO3/DP16B
PIO3/DP16A
GBIN4/PIO2
GBIN5/PIO2
iCE65L08
PIO2
PIO2
Differential inputs swapped, single-ended
I/Os not affected
Differential inputs swapped, single-ended
I/Os not affected
Global buffer input GBIN7 and its
associated differential input is swapped
with another differential pair in I/O
Bank 3
Differential inputs swapped, single-ended
I/Os not affected
Global buffer input GBIN4 swapped with
another PIO pin in I/O Bank 2
Global buffer input GBIN5 swapped with
another PIO pin in I/O Bank 2
Functional Difference
(2.42, 30-MAR-2011)
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