iCE65L04F-LCB284I Lattice, iCE65L04F-LCB284I Datasheet - Page 32

• Manufacturer Part Number: iCE65L04F-LCB284I
• Description: FPGA - Field Programmable Gate Array iCE65 3520 LUTs, 1.0 1.2V Ultra Low-Power
• Manufacturer: Lattice

Specifications of iCE65L04F-LCB284I

• Rohs: yes
• Number Of Gates: 3520
• Number Of Logic Blocks: 20
• Number Of I/os: 176
• Maximum Operating Frequency: 256 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: CBGA-284
• Distributed Ram: 80 Kbit
• Minimum Operating Temperature: - 40 C
• Operating Supply Current: 26 uA
• Factory Pack Quantity: 168

iCE65 Ultra Low-Power mobileFPGA
(2.42, 30-MAR-2012)
32
Figure 25
Low, followed by a Fast Read command, hexadecimal command code 0x0B, followed by a 24-bit start address,
transmitted on the
power-up, the start address is always 0x00_0000. After waiting eight additional clock cycles, the iCE65 device
begins reading serial data from the SPI PROM. Before presenting data, the SPI PROM’s serial data output is high-
impedance. The
The external SPI PROM supplies data on the falling edge of the iCE65 device’s
device captures each PROM data value on the
SPI PROM data starts at the 24-bit address presented by the iCE65 device. PROM data is serially output, byte by
byte, with most-significant bit, D7, presented first. The PROM automatically increments an internal byte counter as
long as the PROM is selected and clocked.
After transferring the required number configuration data bits, the iCE65 device ends the Fast Read command by
de-asserting its
optionally issues a final Deep Power-down command, hexadecimal command code 0xB9. After de-asserting the
SPI_SS_B output, the SPI PROM enters its Deep Power-down mode. The final power-down step is optional; the
application may use the SPI PROM and can skip this step, controlled by a configuration option.
SPI_SS_B
SPI_SCK
SPI_SO
SPI_SI
illustrates the next command issued by the iCE65 device. The iCE65 SPI interface again drives
0 0 0 0 1 0 1 1
Figure 26:
Fast Read
SPI_SS_B
SPI_SI
0x0B
SPI_SO
Figure 24:
input pin has an internal pull-up resistor and sees high-impedance as logic ‘1’.
PROM select output, as shown in
SPI_SS_B
output. The iCE65 device provides data on the falling edge of SPI_SS_B. Upon initial
SPI_SCK
Final Configuration Data, SPI Deep Power-down Command
SPI_SO
SPI_SI
PROM output is Hi-Z. Pulled High in SPI_SI pin via internal pull-up resistor.
Figure 25: SPI Fast Read Command
SPI Release from Deep Power-down Command
SPI_SS_B
SPI_SCK
SPI_SO
24-bit Start Address
Last Data Byte
Fast Read data
SPI_SI
™
Family
input, using the rising edge of the
Release from Deep Power-down
1 0 1 0 1 0 1 1
Figure 26.
0xAB
1 0 1 1 1 0 0
Deep Power-down
To conserve power, the iCE65 device then
X X X X X X X X
0xB9
Lattice Semiconductor Corporation
Don’t Care
Dummy Byte
SPI_SCK
1
SPI_SCK
clock output. The iCE65
Data Byte 0
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clock signal. The
SPI_SS_B