iCE65L04F-LCB284I Lattice, iCE65L04F-LCB284I Datasheet - Page 17

• Manufacturer Part Number: iCE65L04F-LCB284I
• Description: FPGA - Field Programmable Gate Array iCE65 3520 LUTs, 1.0 1.2V Ultra Low-Power
• Manufacturer: Lattice

Specifications of iCE65L04F-LCB284I

• Rohs: yes
• Number Of Gates: 3520
• Number Of Logic Blocks: 20
• Number Of I/os: 176
• Maximum Operating Frequency: 256 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: CBGA-284
• Distributed Ram: 80 Kbit
• Minimum Operating Temperature: - 40 C
• Operating Supply Current: 26 uA
• Factory Pack Quantity: 168

Lattice Semiconductor Corporation
www.latticesemi.com
Double Data Rate (DDR) Flip-Flops
Each individual PIO pin optionally has two sets of double data rate (DDR) flip-flops; one input pair and one output
pair.
device drive the DDR output flip-flop. The D_OUT_0 signal is clocked by the rising edge of the OUTCLK signal
while the D_OUT_1 signal is clocked by the falling edge of the OUTCLK signal, assuming no optional clock polarity
inversion. Internally, the two individual flip-flops are multiplexed together before the data appears at the pad,
effectively doubling the output data rate.
Similarly,
the pad. Internally, one value is clocked by the rising edge of the INCLK signal and another value is clocked by the
falling edge of the INCLK signal. The DDR data stream is effectively de-multiplexed within the PIO pin and
presented to the programmable interconnect on D_IN_0 and D_IN_1.
The DDR flip-flops provide several design advantages. Internally within the iCE65 device, the clock frequency is
half the effective external data rate. The lower clock frequency eases internal timing, doubling the clock period, and
slashes the clock-related power in half.
Figure 12
Figure 13
demonstrates the functionality of the output DDR flip-flop. Two signals from within the iCE65
demonstrates the DDR input flip-flop functionality. A double data rate (DDR) signal arrives at
OUTCLK
D_IN_0
D_IN_1
PAD
D_OUT_1
D_OUT_0
INCLK
INCLK
OUTCLK
IOENA
PAD
IOENA
Figure 12: DDR Output Flip-Flop
Figure 13: DDR Input Flip-Flop
OE
PAD
D0
PIO
D0
D1
D0
D
EN
D
EN
D1
D0
D1
Q
Q
D0
D
EN
D
EN
0
1
D1
D0
S
Q
Q
D1
D0
D1
PIO
D0
D_IN_1
D_IN_0
PAD
D1
D0
D1
D1
(2.42, 30-MAR-2011)
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