PCI-MT32-XP-N1 Lattice, PCI-MT32-XP-N1 Datasheet - Page 86

• Manufacturer Part Number: PCI-MT32-XP-N1
• Description: FPGA - Field Programmable Gate Array PCI Master/Target 32B
• Manufacturer: Lattice

Specifications of PCI-MT32-XP-N1

• Factory Pack Quantity: 1

Lattice Semiconductor
IPUG18_09.2, November 2010
Table 2-30. 32-bit Target Single Write Transaction with a 32-bit Local Interface
CLK
1
2
3
4
5
6
7
Turn around
PCI Data
Address
Phase
Data 1
Wait
Wait
Wait
Idle
The master asserts framen and drives ad[31:0] and cben[3:0].
The master drives the byte enable (Byte Enable 1).The master asserts irdyn, indicating that it is
ready to write the data, and de-asserts framen. To indicate a single data phase transaction, it
drives DWORD (Data 1) on ad[31:0].The Core starts to decode the address and command and
drives the lt_address_out to the back-end.
If an address match is present, the Core drives the bar_hit signals to the back-end. The back-
end can use bar_hit as a chip select.
With the DEVSEL_TIMING set to slow, the Core asserts devseln one clock after bar_hit. If
the back-end will be ready to write data in two cycles, it can assert lt_rdyn.
trdyn is asserted by the Core since lt_rdyn was asserted by the application logic during the
previous cycle.
If both irdyn and trdyn were asserted on the previous cycle, the master relinquishes control of
framen, ad[31:0] and cben[3:0]. The master also de-asserts irdyn since only one data
phase is required. The Core asserts lt_data_xfern to indicate that the valid PCI data is avail-
able for writing.
The Core relinquishes control of devseln and trdyn.The target clears bar_hit to signal to the
back-end that the transaction is complete. It also de-asserts lt_data_xfern.
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Description
Functional Description
PCI IP Core User’s Guide