PCI-MT32-XP-N1 Lattice, PCI-MT32-XP-N1 Datasheet - Page 82

• Manufacturer Part Number: PCI-MT32-XP-N1
• Description: FPGA - Field Programmable Gate Array PCI Master/Target 32B
• Manufacturer: Lattice

Specifications of PCI-MT32-XP-N1

• Factory Pack Quantity: 1

Lattice Semiconductor
Functional Description
• 32-Bit PCI Target with a 32-Bit Local Bus
• 64-Bit PCI Target with a 64-Bit Local Bus
• 32-Bit PCI Target with a 64-Bit Local Bus
Refer to the advanced bus transactions in the Advanced Target Transactions section for more information on proper
wait state insertion and early termination of bus transactions by the PCI IP core.
Design Hint: Using the base address registers as memory space and not I/O space in a device is highly recom-
mended. In a legacy PC environment the I/O space is extremely limited and fragmented due to legacy issues.
32-bit PCI Target with a 32-bit Local Bus Memory Transactions
This section discusses read and write transactions for the PCI IP core, operating as a Target, configured with a 32-
bit PCI bus and a 32-bit local bus. Because 32-bit I/O and memory transactions are alike, they are discussed
together.
Figure 2-24
illustrates an example of a basic 32-bit read transaction.
Table 2-29
gives a clock-by-clock description
of the basic 32-bit transaction in
Figure
2-24. On a read transaction it is important to realize and understand the
latency between the PCI and Local Target Interface. For instance, two clock cycles of latency exist between
lt_rdyn and trdyn.
IPUG18_09.2, November 2010
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PCI IP Core User’s Guide