PCI-MT32-XP-N1 Lattice, PCI-MT32-XP-N1 Datasheet - Page 161

• Manufacturer Part Number: PCI-MT32-XP-N1
• Description: FPGA - Field Programmable Gate Array PCI Master/Target 32B
• Manufacturer: Lattice

Specifications of PCI-MT32-XP-N1

• Factory Pack Quantity: 1

Table B-1. PCI Pins Assignments
IPUG18_09.2, November 2010
Pin Assignment Considerations for LatticeECP and LatticeEC Devices
PCI Pin Assignments for Master/Target 33MHz 64-Bit Bus
The PCI Master/Target 33MHz 64-bit core is optimized for LFEC33E-5F672C. An example assignment, optimized
for best performance, is given in
contained with the .lpf preference file. Refer to the readme file included with the core package for further informa-
tion.
Table
Pin Assignments For Lattice FPGAs
PCI System Pins
PCI Address and Data
Signal Name
B-1. In the IPexpress user-configurable design flow, actual pin assignment is
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rstn
clk
Pin/Bank
AB13/5
AC10/5
AD10/5
AA9/5
AB9/5
AC9/5
AD9/5
AA8/5
AB8/5
AC8/5
AD8/5
AE8/5
AA7/5
AB7/5
AC7/5
AD7/5
AE7/5
AC6/5
AD6/5
AE6/5
AC5/5
AD5/5
AE5/5
AE4/5
AE3/5
AF8/5
AF7/5
AF6/5
AF5/5
AF4/5
W1/6
Y8/5
161
LVCMOS33_IN
Buffer Type
PCI33_BIDI
PCI33_BIDI
PCI33_BIDI
PCI33_BIDI
PCI33_BIDI
PCI33_BIDI
PCI33_BIDI
PCI33_BIDI
PCI33_BIDI
PCI33_BIDI
PCI33_BIDI
PCI33_BIDI
PCI33_BIDI
PCI33_BIDI
PCI33_BIDI
PCI33_BIDI
PCI33_BIDI
PCI33_BIDI
PCI33_BIDI
PCI33_BIDI
PCI33_BIDI
PCI33_BIDI
PCI33_BIDI
PCI33_BIDI
PCI33_BIDI
PCI33_BIDI
PCI33_BIDI
PCI33_BIDI
PCI33_BIDI
PCI33_BIDI
PCI33_IN
PCI IP Core User’s Guide
Appendix B: