PCI-MT32-XP-N1 Lattice, PCI-MT32-XP-N1 Datasheet - Page 45

• Manufacturer Part Number: PCI-MT32-XP-N1
• Description: FPGA - Field Programmable Gate Array PCI Master/Target 32B
• Manufacturer: Lattice

Specifications of PCI-MT32-XP-N1

• Factory Pack Quantity: 1

Lattice Semiconductor
IPUG18_09.2, November 2010
Table 2-16. 32-bit Master Single Write Transaction with a 64-bit Local Interface
CLK
10
11
10
1
2
3
4
5
6
7
8
9
Turn around
Address
Phase
Data 1
Data 2
Wait
Wait
Idle
Idle
Idle
Idle
Idle
Idle
The local master asserts lm_req64n for the master 64-bit data transaction request. It also issues
the PCI starting address, the bus command and the burst length on l_ad_in, lm_cben_in and
lm_burst_length respectively on the same clock cycle.
The Core's Local Master Interface detects the asserted lm_req64n and asserts reqn to request
the use of PCI bus.
gntn is asserted to grant the Core access to the PCI bus. Core is now the PCI master.
Since gntn is asserted and the current bus is idle, the Core is going to start the bus transactions.
The Core asserts lm_gntn to inform the local master that the bus request is granted.
If both lm_req64n and gntn were asserted on the previous cycle, lm_status[3:0] is changed
to ‘Address Loading’ to indicate the starting address, the bus command and the burst length are
being latched.
The local master de-asserts lm_req64n when the previous lm_status[3:0] was ‘Address
Loading’ and if it doesn’t want to request another PCI bus transaction.
The Core asserts framen and req64n to initiate the 64-bit write transaction when gntn was
asserted and lm_status[3:0] was ‘Address Loading’ on the previous cycle. It also drives the
PCI starting address on ad[31:0] and the PCI command on cben[3:0]. On the same cycle, it
outputs lm_status[3:0] as ‘Bus Transaction’ to indicate the beginning of the address/data
phases.
lm_burst_cnt gets the value of the burst length.
Because lm_rdyn was asserted on the previous cycle and the next cycle is the first data phase,
the local master should provide Data 1 and Data 2 on l_ad_in[63:0] and the byte enables on
lm_cben_in[7:0]. The Core asserts lm_ldata_xfern and lm_hdata_xfern to the local
master to signify these data and byte enables are being read and will be transferred to the PCI
bus.
Asserting lm_rdyn means the local master is ready to write data. If it is not, it should keep
lm_rdyn de-asserted until it is ready.
If the target completes the fast decode and is ready to receive 32-bit data, it asserts devseln and
trdyn. But it doesn’t assert ack64n.
The Core de-asserts reqn when framen was asserted and lm_req64n was de-asserted on the
previous cycle.
With lm_data_xfern and lm_hdata_xfern asserted on the previous cycle that was the
address phase, the Core transfers Data 1, Data 2 and the byte enables to ad[63:0] and
cben[7:0].
The Core de-asserts lm_gntn to follow gntn. Since the Core detects the PCI bus transaction
width is 32 bits. It de-asserts lm_64bit_transn and changes lm_burst_cnt to two. The trans-
action is changed from a single cycle to a burst cycle.
With both devseln and lm_rdyn asserted previous cycle, the Core asserts irdyn, and it pre-
pares for the 32-bit write burst.
Because the Core performs the burst transactions, it keeps framen asserted.
Since both irdyn and trdyn are asserted, the first data phase is completed on this cycle.
Since the previous data phase was completed, the Core decreases lm_burst_cnt.
Since Data 1 PCI bus was read by the target, the Core transfers Data 2 and the byte enables to
ad[31:0] and cben[3:0].
With lm_rdyn asserted previous cycle, the Core keeps irdyn asserted. The Core de-asserts
framen for the last data cycle.
Since both irdyn and trdyn are asserted, the second data phase is completed on this cycle.
The Core relinquishes control of framen, req64n, ad and cben. It de-asserts irdyn, decreases
lm_burst_cnt to zero and changes lm_status[3:0] into ‘Bus Termination’ with
lm_termination as ‘Normal Termination’ because both trdyn and irdyn were asserted last
cycle. The target de-asserts devseln and trdyn.
The Core relinquishes control of irdyn par and par64.
45
Description
Functional Description
PCI IP Core User’s Guide