PCI-MT32-XP-N1 Lattice, PCI-MT32-XP-N1 Datasheet - Page 32

• Manufacturer Part Number: PCI-MT32-XP-N1
• Description: FPGA - Field Programmable Gate Array PCI Master/Target 32B
• Manufacturer: Lattice

Specifications of PCI-MT32-XP-N1

• Factory Pack Quantity: 1

Lattice Semiconductor
IPUG18_09.2, November 2010
Figure 2-7. 32-bit Master Single Read Transaction with a 32-Bit Local Interface
lm_burst_length[11:0]
lm_termination[2:0]
lm_burst_cnt[12:0]
l_data_out[31:0]
lm_cben_in[3:0]
lm_data_xfern
lm_status[3:0]
l_ad_in[31:0]
lm_req32n
cben[3:0]
ad[31:0]
lm_gntn
lm_rdyn
devseln
framen
trdyn
irdyn
reqn
gntn
par
clk
1
2
Termination
Bus
3
Bus Length
Command
Don’t care
Address
( = 1 )
Bus
4
Don’t care
Don’t care
5
32
Don’t care
Don’t care
Address
Loading
6
Don’t care
Command
Address
Bus
Byte Enable 1
7
Transaction
Bus Length
Address
Parity
( = 1 )
Bus
Byte Enable 1
8
Don’t care
Don’t care
Data 1
Functional Description
9
PCI IP Core User’s Guide
Don’t care
Parity 1
Data 1
Data
Termination
Termination
10
Normal
Bus
0
Don’t care
11