XRT91L82ES Exar, XRT91L82ES Datasheet - Page 46

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XRT91L82ES

Manufacturer Part Number
XRT91L82ES
Description
Bus Transceivers Transceiver
Manufacturer
Exar
Datasheet

Specifications of XRT91L82ES

Product Category
Bus Transceivers
Rohs
yes
XRT91L82
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
B
D7
D6
D5
D4
D3
D2
IT
PRBS_INV 2
PRBS_EN 2
Reserved
Reserved
Reserved
DLOOP
N
AME
T
ABLE
This Register Bit is Not Used
This Register Bit is Not Used
This bit will invert each of the Pseudo Random Binary Sequence
pattern bit from "0" to "1" and from "1" to "0."
"0" = Normal Operation
"1" = PRBS bit patterns inverted.
Generates 2
and analyzes in the receiving block for correct sequence pattern.
"0" = Normal Mode
"1" = PRBS pattern generator and analyzer Enabled.
N
This Register Bit is Not Used
Digital Local Loopback
Digital local loopback allows the transmit input pins to be looped
back to the receive output pins for local diagnostics. The transmit
serial data output is valid during the digital loopback.
"0" = Enable Digital Local Loopback
"1" = Disabled
N
23
23
OTE
OTE
-1 PRBS Pattern Invert
-1 PRBS TEST Pattern Enable
:
: RLOOPS and RLOOPP should be disabled when DLOOP
19: M
Loopback or an optical cable loopback is expected to be
used in conjunction with PRBS_EN in order for the PRBS
analyzer to receive the PRBS pattern.
is enabled.
A Local Loopback of some type such as Digital Local
ICROPROCESSOR
23
D
-1 Pseudo Random Binary Sequence test patterns
IAGNOSTIC
C
PRELIMINARY
ONTROL
F
UNCTION
R
43
EGISTER
R
EGISTER
0
X
05
(0
H
X
05
B
H
IT
)
D
ESCRIPTION
Register
Type
R/W
R/W
R/W
X
X
X
xr
xr
xr
xr
(HW reset)
REV. P1.0.5
Default
Value
X
X
X
0
0
1

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