XRT91L82ES Exar, XRT91L82ES Datasheet - Page 44

• Manufacturer Part Number: XRT91L82ES
• Description: Bus Transceivers Transceiver
• Manufacturer: Exar

Specifications of XRT91L82ES

• Product Category: Bus Transceivers
• Rohs: yes

XRT91L82
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
B
D7
D6
D5
D4
D3
D2
D1
D0
IT
AUTORST
FIFO_RST
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
FIFO_
N
AME
T
ABLE
This Register Bit is Not Used
This Register Bit is Not Used
This Register Bit is Not Used
This Register Bit is Not Used
This Register Bit is Not Used
This Register Bit is Not Used
Automatic FIFO Overflow Reset
If this bit is set to "1", the STS-48 transceiver will automatically
flush the FIFO upon an overflow condition. Upon power-up, the
FIFO should be manually reset by setting FIFO_RST to "1" for a
minimum of 2 TXPCLKOP/N cycles.
"0" = Manual FIFO reset required for Overflow Conditions
"1" = Automatically resets FIFO upon Overflow Detection
Manual FIFO Reset
FIFORST should be set to "1" for a minimum of 2 TXPCLKOP/N
cycles during power-up and manual FIFO reset in order to flush out
the FIFO. After the FIFORST bit is returned "Low," it will take 8 to
10 TXPCLKOP/N cycles for the FIFO to flush out. Upon an inter-
rupt indication that the FIFO has an overflow condition, this bit is
used to reset or flush out the FIFO.
"0" = Normal Operation
"1" = Manual FIFO Reset
N
OTE
: To automatically reset the FIFO, see the FIFO_AUTORST
17: M
bit.
ICROPROCESSOR
FIFO C
ONTROL
PRELIMINARY
F
UNCTION
R
41
R
EGISTER
EGISTER
0
(0
X
X
03
03
H
H
)
B
IT
D
ESCRIPTION
Register
Type
R/W
R/W
X
X
X
X
X
X
xr
xr
xr
xr
(HW reset)
REV. P1.0.5
Default
Value
X
X
X
X
X
X
0
0