XRT91L82ES Exar, XRT91L82ES Datasheet - Page 38
![no-image](/images/no-image-200.jpg)
XRT91L82ES
Manufacturer Part Number
XRT91L82ES
Description
Bus Transceivers Transceiver
Manufacturer
Exar
Datasheet
1.XRT91L82ES.pdf
(59 pages)
Specifications of XRT91L82ES
Product Category
Bus Transceivers
Rohs
yes
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XRT91L82
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
The serial microprocessor uses a standard 3-pin serial port with CS, SCLK, and SDI for programming the
transceiver. Optional pins such as SDO, INT, and RESET allow the ability to read back contents of the
registers, monitor the transceiver via an interrupt pin, and reset the transceiver to its default configuration by
pulling reset "Low" for more than 30ns. A simplified block diagram of the Serial Microprocessor is shown in
Figure 28.
F
The serial port requires 16 bits of data applied to the SDI (Serial Data Input) pin. The Serial Microprocessor
samples SDI on the rising edge of SCLK (Serial Clock Input). The data is not latched into the device until all 16
bits of serial data have been sampled. A timing diagram of the Serial Microprocessor is shown in Figure 29.
F
N
5.0 SERIAL MICROPROCESSOR INTERFACE BLOCK
5.1 S
IGURE
IGURE
OTE
: The serial microprocessor interface does NOT support "burst write" or "burst read" operations. Chip Select (active
SCLK
SDO
"Low") must be de-asserted at the end of every single write or single read operation.
ERIAL
SDI
28. S
29. T
CS
IMING
IMPLIFIED
T
IMING
D
25nS
HW/Host
I
IAGRAM FOR THE
NFORMATION
R/W
B
SCLK
1
LOCK
SDI
CS
A0
2
D
IAGRAM OF THE
A1
3
50nS
High-Z
A2
S
4
ERIAL
A3
RESET
5
Microprocessor
M
A4
ICROPROCESSOR
S
6
PRELIMINARY
Interface
ERIAL
Serial
A5
7
35
M
X
ICROPROCESSOR
8
D0
D0
9
I
NTERFACE
D1
D1
10
D2
D2
11
I
NTERFACE
D3
D3
12
SDO
D4
D4
INT
13
D5
D5
14
D6
D6
15
xr
xr
xr
xr
D7
D7
16
REV. P1.0.5
High-Z
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