XRT91L82ES Exar, XRT91L82ES Datasheet - Page 21

• Manufacturer Part Number: XRT91L82ES
• Description: Bus Transceivers Transceiver
• Manufacturer: Exar

Specifications of XRT91L82ES

• Product Category: Bus Transceivers
• Rohs: yes

xr
xr
xr
xr
REV. P1.0.5
The receive section of XRT91L82 includes the differential inputs RXIP/N, followed by the clock and data
recovery unit (CDR) and receive serial-to-parallel converter. The receiver accepts the high-speed Non-Return
to Zero (NRZ) serial data at 2.488/2.666 Gbps through the differential input interfaces RXIP/N. The clock and
data recovery unit recovers the high-speed receive clock from the incoming scrambled NRZ data stream. The
recovered serial data is converted into 16-bit-wide 155.52/166.63 Mbps parallel data and presented to the
RXDO[15:0]P/N parallel interface. This parallel interface can be configured for Differential LVPECL/LVDS, or
Single-Ended LVPECL operation. A divide-by-16 version of the high-speed recovered clock, RXPCLKOP/N is
used to synchronize the transfer of the 16-bit RXDO[15:0]P/N data with the receive portion of the upstream
device. Upon initialization or loss of signal or loss of lock the 155.52 MHz or 166.63 MHz external local
reference clock is used to start-up the clock recovery phase-locked loop for proper operation. In Host Mode, a
special loopback feature can be configured when parallel remote loopback (RLOOPP) is used in conjunction
with de-jittered loop-time mode that allows the re-transmitted data to comply with ITU and Bellcore jitter
generation specifications.
The receive serial CML inputs are applied to RXIP/N. The receive serial inputs can be AC or DC coupled to an
optical module or an electrical interface. A simplified AC coupled block diagram is shown in Figure 4.
F
N
The 2.488/2.666 Gbps high-speed differential CML RXIP/N input swing characteristics is shown in Table 4.
Figure 17, “CML Differential Voltage Swing,” on page 29 shows the CML differential voltage swing.
2.0 RECEIVE SECTION
2.1
IGURE
OTE
R
V
V
V
DIFF
: Some optical modules integrate AC coupled capacitors within the module. If so, the external AC coupled capacitors
INDIFF
INSE
INBIAS
P
ARAMETER
are not necessary and can be excluded.
4. R
Receive Serial Input
ECEIVE
S
Differential Input Voltage Swing
Single-Ended Input Voltage Swing
Input Bias Range (AC Coupled)
Differential Input Resistance
ERIAL
Transceiver
XRT91L82
STS-48/
STM-16
I
T
NPUT
ABLE
RXIP
RXIN
D
ESCRIPTION
I
NTERFACE
4: D
IFFERENTIAL
0.1 F
0.1 F
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
PRELIMINARY
B
LOCK
CML I
Optical Module
18
VDD_CML - 0.4
NPUT
100
M
S
50
80
IN
WING
P
ARAMETERS
100
T
Optical Fiber
YP
VDD_CML - 0.2
2000
1000
M
120
AX
XRT91L82
U
mV
mV
NITS
V