XRT91L82ES Exar, XRT91L82ES Datasheet
XRT91L82ES
Specifications of XRT91L82ES
Related parts for XRT91L82ES
XRT91L82ES Summary of contents
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... SONET/SDH Test Equipment DWDM Termination Equipment PISO Re-Timer (Parallel Input Serial Output) CMU DLOOP RLOOPS SIPO (Serial Input CDR Parallel Output) Hardware Control • • (510) 668-7000 FAX (510) 668-7017 XRT91L82 REV. P1.0.5 TXOP/N TXSCLKOP/N RXIP/N PFD & Charge Pump • www.exar.com ...
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XRT91L82 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER FEATURES 2.488 / 2.666 Gbps Transceiver Targeted for SONET OC-48/SDH STM-16 Applications Selectable full duplex operation between standard rate of 2.488 Gbps or Forward Error Correction rate of 2.666 Gbps Single-chip fully integrated solution ...
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A GND RXIP RXIN VDD_CML TXON B GND GND VDD_CML GND VDD_CML C AVDD_RX SDEXT SEREFDIS TXCLKO16SEL LOCKDET_CDR LOCKDET_CMU DISRD D GND AVDD_RX PIO_CFG1 FIFO_RST /PRBS_LOCK INTERM E RXCAP1P GND PIO_CFG0 RESET / VCXO_IN RXCAP1N F GND VDD_CMOS GND VDD_CMOS ...
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XRT91L82 REV. P1.0.5 GENERAL DESCRIPTION .................................................................................................1 APPLICATIONS ........................................................................................................................................... XRT91L82 ...................................................................................................................................... 1 IGURE LOCK IAGRAM OF ......................................................................................................................................................2 FEATURES PRODUCT ORDERING INFORMATION .................................................................................................. 196 BGA P THE XRT91L82 (T IGURE INOUT ............................................................................................................ ABLE ...
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GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER 3.6 CLOCK MULTIPLIER UNIT (CMU) AND RE-TIMER ..................................................................................... ABLE LOCK ULTIPLIER NIT 3.7 LOOP TIMING AND CLOCK CONTROL ....................................................................................................... 26 T 11: L ABLE ...
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XRT91L82 REV. P1.0 1.00.......................................................................................................................................... .......................................................................................................................................54 EVISION ISTORY PRELIMINARY 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER III ...
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REV. P1.0.5 PIN DESCRIPTIONS COMMON CONTROL N L AME EVEL RESET LVTTL, LVCMOS PIO_CFG1 LVTTL, PIO_CFG0 LVCMOS XRES1P - XRES1N SE_REF Analog SEREFDIS LVTTL, LVCMOS REF1CLKP LVPECL Diff REF1CLKN PRELIMINARY 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER T ...
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XRT91L82 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER COMMON CONTROL AME EVEL REF2CLKP LVPECL Diff REF2CLKN REFREQSEL1 LVTTL, / SCLK LVCMOS REFREQSEL0 LVTTL, LVCMOS PRELIMINARY P YPE IN I A11 Reference Clock Input 2 B11 This differential clock input ...
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REV. P1.0.5 COMMON CONTROL AME EVEL PRBS_EN LVTTL, LVCMOS PRBS_ERR LVCMOS /SDO RLOOPS_ - LVTTL, PRBSCLR LVCMOS PRELIMINARY 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER P YPE PRBS TEST ...
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XRT91L82 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER COMMON CONTROL N L AME EVEL DLOOP LVTTL, LVCMOS LOOPTM_NOJA LVTTL, / SDI LVCMOS PRELIMINARY T P YPE IN I E11 Digital Local Loopback The digital local loopback mode interconnects the 16-bit parallel transmit ...
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REV. P1.0.5 TRANSMITTER SECTION AME EVEL TXDI0P LVDS, TXDI0N LVPECL TXDI1P Diff and SE TXDI1N TXDI2P TXDI2N TXDI3P TXDI3N TXDI4P TXDI4N TXDI5P TXDI5N TXDI6P TXDI6N TXDI7P TXDI7N TXDI8P TXDI8N TXDI9P TXDI9N TXDI10P TXDI10N ...
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XRT91L82 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER TRANSMITTER SECTION AME EVEL TXSCLKOP CMLDIFF TXSCLKON TXSCLKOOFF LVTTL LVCMOS INTERM LVTTL, / VCXO_IN LVCMOS / SE- LVCMOS TXPCLKIP LVDS, TXPCLKIN LVPECL Diff and SE TXPCLKOP LVDS, TXPCLKON LVPECL ...
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REV. P1.0.5 TRANSMITTER SECTION AME EVEL TXCLKO16P LVDS, TXCLKO16N LVPECL Diff and SE TXCLKO16SEL LVTTL, LVCMOS LOCKDET_CMU LVCMOS OVERFLOW LVCMOS FIFO_RST LVTTL, LVCMOS PRELIMINARY 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER P YPE IN O ...
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XRT91L82 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER RECEIVER SECTION N L AME EVEL RXDO0P LVDS, RXDO0N LVPECL RXDO1P Diff and SE RXDO1N RXDO2P RXDO2N RXDO3P RXDO3N RXDO4P RXDO4N RXDO5P RXDO5N RXDO6P RXDO6N RXDO7P RXDO7N RXDO8P RXDO8N RXDO9P RXDO9N RXDO10P RXDO10N RXDO11P ...
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REV. P1.0.5 RECEIVER SECTION N L AME EVEL CDRLCKREF LVTTL, LVCMOS DISRD LVTTL, /PRBS_LOCK LVCMOS DISRDCLK LVTTL, LVCMOS LOCKDET_CDR LVCMOS SDEXT LVTTL, LVCMOS POLARITY LVTTL, LVCMOS PRELIMINARY 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER T P YPE IN ...
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XRT91L82 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER RECEIVER SECTION AME EVEL RXCAP1P Analog RXCAP1N Analog / CP_OUT POWER AND GROUND N T AME YPE AVDD_RX PWR C1, D2, G2, H1 AVDD_TX PWR C14, D13, G13, H14 VDD_CML PWR ...
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REV. P1.0.5 SERIAL MICROPROCESSOR INTERFACE AME EVEL HOST/HW LVTTL, LVCMOS TXSCLKOOFF LVTTL LVCMOS REFREQSEL1 LVTTL, / SCLK LVCMOS LOOPTM_NOJA LVTTL, / SDI LVCMOS PRBS_ERR LVCMOS / SDO TXSWING LVCMOS / INT ...
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XRT91L82 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER JTAG IGNAL AME IN YPE TCK C7 I TMS D8 I TDI C8 I TDO D7 O TRST CONNECTS AME EVEL YPE None ...
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REV. P1.0.5 1.0 FUNCTIONAL DESCRIPTION The XRT91L82 Transceiver is designed to operate with a SONET Framer/ASIC device and provide a high- speed serial interface to optical networks. The Transceiver converts 16-bit parallel data at 155.52/166.63 MHz ...
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XRT91L82 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER ABLE LTERNATE CMU R CDR R EFERENCE REFREQSEL C LOCK [1: REQUENCY 00 REF1CLK 01 REF1CLK 10 REF2CLK 11 REF2CLK 1.4 Data Latency Due to different operating modes and ...
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REV. P1.0.5 2.0 RECEIVE SECTION The receive section of XRT91L82 includes the differential inputs RXIP/N, followed by the clock and data recovery unit (CDR) and receive serial-to-parallel converter. The receiver accepts the high-speed Non-Return to Zero ...
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XRT91L82 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER 2.2 External Receive Loop Filter Capacitors These external loop filter 0 resistors and 22 F non-polarized capacitor provide the necessary components to achieve the required receiver jitter performance. They must be well isolated to ...
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REV. P1.0 ABLE N AME REF Reference clock duty cycle DUTY REF Reference clock frequency tolerance TOL OCLK Clock output jitter generation with 155.52 MHz reference clock JIT OCLK Clock output jitter generation ...
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XRT91L82 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER 2.5 Receive Serial Input to Parallel Output (SIPO) The SIPO is used to convert the 2.488/2.666 Gbps serial data input to 155.52/166.63 Mbps parallel data output which can interface to a SONET Framer/ASIC. The ...
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REV. P1.0.5 2.7 Receive Parallel Interface LVDS Operation When operating the 16-bit Differential bus in LVDS mode, a 402 and XRES1N to properly bias the RXDO[15:0]P/N and RXPCLKOP/N pins. Figure 8 shows the proper biasing resistor ...
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XRT91L82 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER 3.0 TRANSMIT SECTION The transmit section of the XRT91L82 accepts 16-bit parallel data and converts it to serial CML data output intented to interface to an optical module. It consists of a 16-bit parallel ...
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REV. P1.0.5 3.2 Transmit Parallel Data Input Timing When applying parallel data input to the transmitter, the setup and hold times should be followed as shown in Figure 11 and Table 8. Table 9 shows the ...
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XRT91L82 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER In Host Mode, the transceiver under the control of the FIFO_AUTORST register bit can automatically recover from an overflow condition. When the FIFO_AUTORST register bit is set to a "High" level, once an overflow ...
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REV. P1.0.5 3.6 Clock Multiplier Unit (CMU) and Re-Timer The high-speed serial clock synthesized by the CMU is divided by 16 and is then presented to the upstream device as TXPCLKOP/N clock. The upstream device should ...
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XRT91L82 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER The on-chip phase/frequency detector can also be used to remove the jitter from a noisy reference signal that is applied to the REF1CLKP/N or REF2CLKP/N inputs. In this case the LOOPTM_NOJA register bit should ...
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REV. P1.0.5 3.8 External Loop Filter (Host Mode Only) During Host Mode operation, RXCAP1N becomes the charge pump output CP_OUT. As shown in Figure 14, the internal charge pump is used to drive an external loop ...
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XRT91L82 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER T 12: D ABLE IGNAL YPE ARAMETER Clock V OUTDIFF Clock V OUTSE Data V OUTDIFF Data V OUTSE F 17. CML D V IGURE IFFERENTIAL OLTAGE V(+) V(-) V(+) - ...
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REV. P1.0.5 4.0 DIAGNOSTIC FEATURES 4.1 Serial Remote Loopback RLOOPS_PRBSCLR is a dual function pin that serves as both serial remote loopback enable and PRBS error clear function. The serial remote loopback function is activated by ...
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XRT91L82 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER 4.3 Digital Local Loopback The digital local loopback is activated when the DLOOP signal is set "Low." When digital local loopback is activated, the high-speed data from the output of the parallel to serial ...
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REV. P1.0.5 4.4 SONET Jitter Requirements SONET equipment jitter requirements are specified for the following three types of jitter. The definitions of each of these types of jitter are given below. SONET equipment jitter requirements are ...
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XRT91L82 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER F 22. XRT91L82 M IGURE EASURED F 23. XRT91L82 M IGURE EASURED 4.4.2 Jitter Transfer Jitter transfer is defined as the ratio of the jitter on the output of STS-N to the jitter applied ...
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REV. P1.0.5 4.4.3 Jitter Generation Jitter generation is defined as the amount of jitter at the STS-N output in the absence of applied input jitter. The Bellcore and ITU requirement for this type jitter is 0.01UI ...
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XRT91L82 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER 5.0 SERIAL MICROPROCESSOR INTERFACE BLOCK The serial microprocessor uses a standard 3-pin serial port with CS, SCLK, and SDI for programming the transceiver. Optional pins such as SDO, INT, and RESET allow the ability ...
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REV. P1.0.5 5.2 16 ERIAL ATA NPUT ESCRITPTION The serial data input is sampled on the rising edge of SCLK. In readback mode, the serial data output is updated on the ...
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XRT91L82 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER 6.0 REGISTER MAP AND BIT DESCRIPTIONS T ABLE R ADDR YPE Control Registers (0x00h - 0x3Fh) 0 0x00 R/W Reserved PRBSLIE 1 0x01 RUR Reserved PRBSLIS 2 0x02 RO Reserved PRBS_LOCK ...
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REV. P1.0.5 T 14: M ABLE I NTERRUPT AME D7 Reserved This Register Bit is Not Used D6 PRBSLIE PRBS Pattern Lock Interrupt Enable "0" = Masks the PRBS Pattern ...
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XRT91L82 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER T 15: M ABLE I NTERRUPT AME D7 Reserved This Register Bit is Not Used D6 PRBSLIS PRBS Pattern Lock Interrupt Status An external interrupt will not occur ...
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REV. P1.0.5 T 16: M ABLE AME D7 Reserved This Register Bit is Not Used D6 PRBS_LOCK PRBS Pattern Lock Detection Indicates that current state condition of the PRBS pattern ...
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XRT91L82 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER T 17: M ABLE AME D7 Reserved This Register Bit is Not Used D6 Reserved This Register Bit is Not Used D5 Reserved This Register Bit is Not Used D4 Reserved ...
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REV. P1.0.5 T 18: M ABLE AME D7 Reserved This Register Bit is Not Used D6 Reserved This Register Bit is Not Used D5 Reserved This Register Bit is Not Used D4 Reserved ...
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XRT91L82 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER T 19: M ABLE AME D7 Reserved This Register Bit is Not Used D6 Reserved This Register Bit is Not Used D5 PRBS_INV PRBS Pattern Invert This bit ...
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REV. P1.0 AME D1 RLOOPS Serial Remote Loopback Serial remote loopback allows the receive serial input pins to be looped back to the transmit serial output pins for remote diagnos- tics. The receive ...
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XRT91L82 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER T 20: M ABLE AME D7 VCXOLKEN De-Jitter PLL Lock Detect Enable This bit enables the VCXO_IN input lock detect circuit to be active. "0" = VCXO Lock Detect Disabled "1" ...
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REV. P1.0.5 T 21: M ABLE AME D7 REFREQSEL1 Input Reference Frequency Select This bit is used to select the clock input reference. REFREQSEL [1: Note: Non-FEC transmission and/or ...
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XRT91L82 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER AME D5 ALTFREQSEL Alternate Low Reference Frequency Select (77.76/83.31 MHz) This pin is used to select and support lower frequency settings on REF1CLKP/N and REF2CLKP/N reference clock inputs. When using a ...
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REV. P1.0 AME D3 INTERM Transmit Parallel Bus Input Internal Termination Provides 100 line-to-line internal termination to TXDI[15:0]P/N and TXPCLKIP/N. "Low" = Disabled "High" = TXDI[15:0]P/N and TXPCLKIP/N internally terminated. D2 SEREFDIS SE_REF ...
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XRT91L82 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER T 23: M ABLE AME D7 Device "ID" The device "ID" of the XRT91L82 LIU is 0x8003h. Along with the revision "ID", the device "ID" is used to enable software to ...
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REV. P1.0.5 7.0 ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Thermal Resistance of STBGA Package.... Thermal Resistance of STBGA Package.... ESD Protection (HBM)..........................................>2000V ABSOLUTE MAXIMUM POWER AND INPUT LOGIC SIGNALS S T YMBOL YPE VDD 1.8V Digital and ...
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XRT91L82 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER POWER AND CURRENT DC ELECTRICAL CHARACTERISTICS S T YMBOL YPE P Total Power Dissipation LVDS P Total Power Dissipation LVPECL LVPECL LOGIC SIGNAL DC ELECTRICAL CHARACTERISTICS Test Condition 25° C, VDD = ...
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REV. P1.0.5 Test Condition 25° C, VDD = 1.8V + 5%, VDD A 1 YMBOL YPE ARAMETER V LVDS Input Low Voltage IL V LVDS Input Differential Voltage IDIFF Swing V ...
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XRT91L82 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER P N ART UMBER XRT91L82IB 196 Shrink Thin Ball Grid Array (15 15.0 mm, STBGA) 196 SHRINK THIN BALL GRID ARRAY D Seating Plane A2 A1 Note: The control dimension is in ...
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REV. P1.0.5 REVISION HISTORY EVISION ATE P1.0.0 November 2004 Preliminary XRT91L82 datasheet. P1.0.1 December 2004 Fixed pin-out discrepancies. P1.0.2 January 2005 1.Added CS de-assertion note on section 5.1. 2.Updated all registers and fixed ...
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XRT91L82 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER REVISION HISTORY EVISION ATE P1.0.3 March 2005 1.Moved microprocessor SDI pin from D10 to pin C10 and SCLK from D4 to pin D12. 2.Moved CP_OUT from pin F14 pin to pin ...
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... Figure 14 Loop Timing Mode Using an External Cleanup VCXO. 10.Revised and Updated Electrical Characteristics section 7.0 EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’ ...