XRT91L82ES Exar, XRT91L82ES Datasheet - Page 26

• Manufacturer Part Number: XRT91L82ES
• Description: Bus Transceivers Transceiver
• Manufacturer: Exar

Specifications of XRT91L82ES

• Product Category: Bus Transceivers
• Rohs: yes

XRT91L82
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
The transmit section of the XRT91L82 accepts 16-bit parallel data and converts it to serial CML data output
intented to interface to an optical module. It consists of a 16-bit parallel Differential LVPECL/LVDS, or Single-
Ended LVPECL interface, a 16x9 FIFO, Parallel-to-Serial Converter, a clock multiplier unit (CMU), a Current
Mode Logic (CML) differential line driver, and Loop Timing modes. The CML serial data output rate is 2.488/
2.666 Gbps for STS-48 applications. The high frequency serial clock is synthesized by a PLL, which uses a low
frequency clock as its input reference. In order to synchronize the data transfer process, the synthesized
2.488/2.666 GHz serial clock output is divided by sixteen and the 155.52/166.63 MHz clock is presented to the
upstream device to be used as its timing source.
The parallel data from an upstream device is presented to the XRT91L82 through a 16-bit Differential LVPECL/
LVDS/Single-Ended LVPECL parallel bus interface TXDI[15:0]P/N. The data is latched into a parallel input
register on the rising edge of TXPCLKIP/N. If the SONET Framer/ASIC is synchronized to the same timing
source as the XRT91L82, the transmit data and clock input can directly interface to the STS-48/STM-16
transceiver. However, if the SONET Framer/ASIC is synchronized to a separate crystal, the XRT91L82 has
two clock output references that can be used to synchronize the SONET Framer/ASIC. TXPCLKOP/N is a
155.52/166.63 MHz Differential LVPECL/LVDS or Single-Ended LVPECL clock output source that is derived
from the CMU synthesized clock. TXCLKO16P/N is a 155.52/166.63 MHz or 19.44/20.83 MHz Differential
LVPECL/LVDS or Single-Ended LVPECL auxiliary clock output source that is also derived from the CMU
sythensized clock. Either of these two clock output sources can be used to synchronize the SONET Framer/
ASIC to the XRT91L82. A simplified block diagram of the parallel interface is shown in Figure 10.
F
3.0 TRANSMIT SECTION
3.1
IGURE
10. T
Transmit Parallel Interface
RANSMIT
P
ARALLEL
SONET Framer/ASIC
I
NPUT
I
NTERFACE
TXDI[15:0]P/N
TXPCLKIP/N
PRELIMINARY
B
LOCK
16
23
TXPCLKOP/N
TXCLKO16P/N
STS-48/STM-16
Transceiver
TXCLKO16SEL
XRT91L82
xr
xr
xr
xr
REV. P1.0.5