LPC1113FHN33/303,5 NXP Semiconductors, LPC1113FHN33/303,5 Datasheet - Page 372

• Manufacturer Part Number: LPC1113FHN33/303,5
• Description: ARM Microcontrollers - MCU Cortex-M0 24 kB flash up to 8kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1113FHN33/303,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1113
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 24 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
Table 329: Interrupt Register (TMR32B0IR - address 0x4001 4000 and TMR32B1IR - address 0x4001 8000) bit
UM10398
User manual
Bit
0
1
2
3
4
5
31:6
description
Symbol
MR0INT
MR1INT
MR2INT
MR3INT
CR0INT
CR1INT
-
21.7.1 Interrupt Register (TMR32B0IR and TMR32B1IR)
21.7.2 Timer Control Register (TMR32B0TCR and TMR32B1TCR)
21.7.3 Timer Counter (TMR32B0TC - address 0x4001 4008 and
The Interrupt Register consists of four bits for the match interrupts and one bit for the
capture interrupts. If an interrupt is generated then the corresponding bit in the IR will be
HIGH. Otherwise, the bit will be LOW. Writing a logic one to the corresponding IR bit will
reset the interrupt. Writing a zero has no effect.
The Timer Control Register (TCR) is used to control the operation of the counter/timer.
Table 330: Timer Control Register (TMR32B0TCR - address 0x4001 4004 and TMR32B1TCR -
TMR32B1TC - address 0x4001 8008)
The 32-bit Timer Counter is incremented when the Prescale Counter reaches its terminal
count. Unless it is reset before reaching its upper limit, the TC will count up through the
value 0xFFFF FFFF and then wrap back to the value 0x0000 0000. This event does not
cause an interrupt, but a Match register can be used to detect an overflow if needed.
Table 331: Timer counter registers (TMR32B0TC, address 0x4001 4008 and TMR32B1TC
Bit
0
1
31:2
Bit
31:0
Description
Interrupt flag for match channel 0.
Interrupt flag for match channel 1.
Interrupt flag for match channel 2.
Interrupt flag for match channel 3.
Reserved
Interrupt flag for capture channel 0 event.
Interrupt flag for capture channel 1 event.
Symbol
CEN
CRST
-
Symbol
TC
address 0x4001 8004) bit description
0x4001 8008) bit description
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 24 September 2012
Chapter 21: LPC1100XL series: 32-bit counter/timer CT32B0/1
Description
Timer counter value.
Description
When one, the Timer Counter and Prescale Counter are
enabled for counting. When zero, the counters are
disabled.
When one, the Timer Counter and the Prescale Counter
are synchronously reset on the next positive edge of
PCLK. The counters remain reset until TCR[1] is
returned to zero.
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
UM10398
© NXP B.V. 2012. All rights reserved.
Reset value
0
0
0
0
0
0
-
Reset value
0
0
NA
372 of 538
Reset
value
0