LPC1113FHN33/303,5 NXP Semiconductors, LPC1113FHN33/303,5 Datasheet - Page 160
LPC1113FHN33/303,5
Manufacturer Part Number
LPC1113FHN33/303,5
Description
ARM Microcontrollers - MCU Cortex-M0 24 kB flash up to 8kB SRAM
Manufacturer
NXP Semiconductors
Datasheet
1.LPC1113FHN333035.pdf
(538 pages)
Specifications of LPC1113FHN33/303,5
Rohs
yes
Core
ARM Cortex M0
Processor Series
LPC1113
Data Bus Width
32 bit
Maximum Clock Frequency
50 MHz
Program Memory Size
24 KB
Data Ram Size
4 KB
On-chip Adc
Yes
Operating Supply Voltage
1.8 V to 3.6 V
Operating Temperature Range
- 65 C to + 150 C
Package / Case
HVQFN-33
Mounting Style
SMD/SMT
Factory Pack Quantity
260
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NXP Semiconductors
Table 163. LPC11D14 pin description table (LQFP100 package)
[1]
[2]
[3]
[4]
[5]
[6]
[7]
UM10398
User manual
Symbol
S38
S39
BP0
BP1
BP2
BP3
LCD_SDA
LCD_SCL
SYNC
CLK
V
V
V
n.c.
DD(LCD)
SS(LCD)
LCD
Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled (pins pulled up to full V
IA = inactive, no pull-up/down enabled.
RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to reset the chip and wake up from Deep
power-down mode. An external pull-up resistor is required on this pin for the Deep power-down mode.
5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis.
I
5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input.
When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant.
When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded
(grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating.
See the LPC11D4 data sheet.
2
C-bus pads compliant with the I
Pin
33
34
42
44
43
45
35
36
37
38
39
40
41
3
Start
logic
input
-
-
-
-
-
-
-
-
-
-
-
-
-
-
2
C-bus specification for I
Chapter 9: LPC111x/LPC11Cxx Pin configuration (LPC1100, LPC1100C,
Type
O
O
O
O
O
O
I/O
I/O
I/O
I/O
-
-
-
-
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 24 September 2012
Reset
state
[1]
V
V
V
V
V
V
[7]
[7]
[7]
[7]
-
-
-
-
LCD
LCD
LCD
LCD
LCD
LCD
2
C standard mode and I
[7]
[7]
[7]
[7]
[7]
[7]
Description
LCD segment output.
LCD segment output.
LCD backplane output.
LCD backplane output.
LCD backplane output.
LCD backplane output.
I
I
Cascade synchronization input/output.
External clock input/output.
1.8 V to 5.5 V power supply: Power supply voltage for the
PCF8576D.
LCD ground.
LCD power supply; LCD voltage.
Not connected.
2
2
C-bus serial data input/output.
C-bus serial clock input.
…continued
2
C Fast-mode Plus.
UM10398
DD
© NXP B.V. 2012. All rights reserved.
level (V
DD
160 of 538
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