LPC1113FHN33/303,5 NXP Semiconductors, LPC1113FHN33/303,5 Datasheet - Page 231
LPC1113FHN33/303,5
Manufacturer Part Number
LPC1113FHN33/303,5
Description
ARM Microcontrollers - MCU Cortex-M0 24 kB flash up to 8kB SRAM
Manufacturer
NXP Semiconductors
Datasheet
1.LPC1113FHN333035.pdf
(538 pages)
Specifications of LPC1113FHN33/303,5
Rohs
yes
Core
ARM Cortex M0
Processor Series
LPC1113
Data Bus Width
32 bit
Maximum Clock Frequency
50 MHz
Program Memory Size
24 KB
Data Ram Size
4 KB
On-chip Adc
Yes
Operating Supply Voltage
1.8 V to 3.6 V
Operating Temperature Range
- 65 C to + 150 C
Package / Case
HVQFN-33
Mounting Style
SMD/SMT
Factory Pack Quantity
260
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NXP Semiconductors
UM10398
User manual
14.7.3.1 Setup and hold time requirements on CS with respect to SK in Microwire
turn latches each bit on the rising edge of SK. At the end of the frame, for single transfers,
the CS signal is pulled HIGH one clock period after the last bit has been latched in the
receive serial shifter, that causes the data to be transferred to the receive FIFO.
Note: The off-chip slave device can tristate the receive line either on the falling edge of
SK after the LSB has been latched by the receive shiftier, or when the CS pin goes HIGH.
For continuous transfers, data transmission begins and ends in the same manner as a
single transfer. However, the CS line is continuously asserted (held LOW) and
transmission of data occurs back to back. The control byte of the next frame follows
directly after the LSB of the received data from the current frame. Each of the received
values is transferred from the receive shifter on the falling edge SK, after the LSB of the
frame has been latched into the SPI/SSP.
mode
In the Microwire mode, the SPI/SSP slave samples the first bit of receive data on the
rising edge of SK after CS has gone LOW. Masters that drive a free-running SK must
ensure that the CS signal has sufficient setup and hold margins with respect to the rising
edge of SK.
Figure 43
edge on which the first bit of receive data is to be sampled by the SPI/SSP slave, CS must
have a setup of at least two times the period of SK on which the SPI/SSP operates. With
respect to the SK rising edge previous to this edge, CS must have a hold of at least one
SK period.
Fig 43. Microwire frame format setup and hold details
illustrates these setup and hold time requirements. With respect to the SK rising
All information provided in this document is subject to legal disclaimers.
CS
SK
SI
Rev. 12 — 24 September 2012
Chapter 14: LPC111x/LPC11Cxx SPI0/1 with SSP
t
HOLD
= t
SK
t
SETUP
=2*t
SK
UM10398
© NXP B.V. 2012. All rights reserved.
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