IS42S16100E-6BLI-TR ISSI, IS42S16100E-6BLI-TR Datasheet - Page 36

• Manufacturer Part Number: IS42S16100E-6BLI-TR
• Description: DRAM 16M 1Mx16 166Mhz SDRAM, 3.3v
• Manufacturer: ISSI

Specifications of IS42S16100E-6BLI-TR

• Rohs: yes
• Data Bus Width: 16 bit
• Organization: 1 Mbit x 16
• Package / Case: BGA-60
• Memory Size: 16 Mbit
• Maximum Clock Frequency: 166 MHz
• Access Time: 6 ns
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 3 V
• Maximum Operating Current: 180 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 1000

36
IS42S16100E, IS45S16100E
Write Cycle (Full Page) Interruption Using
the Burst Stop Command
The IS42/4516100E can input data continuously from
the burst start address (a) to location a+255 during a
write cycle in which the burst length is set to full page.
The IS42/4516100E repeats the operation starting at
the 256th cycle with data input returning to location (a)
and continuing with a+1, a+2, a+3, etc. A burst stop
command must be executed to terminate this cycle. A
precharge command
Burst Data Interruption Using the U/LDQM
Pins (Read Cycle)
Burst data output can be temporarily interrupted (masked)
during a read cycle using the U/LDQM pins. Regardless of
the CAS latency, two clock cycles (t
U/LDQM pins goes HIGH, the corresponding outputs go
to the HIGH impedance state. Subsequently, the outputs
are maintained in the high impedance state as long as
that U/LDQM pin remains HIGH. When the U/LDQM pin
goes LOW, output is resumed at a time t
CAS latency = 2, burstlength = 4
COMMAND
COMMAND
CLK
DQ8-DQ15
DQ
DQ0-DQ 7
UDQM
LDQM
READ (CA=A, BANK 0)
CLK
WRITE A0
D
IN
READ (CA=A, BANK 0)
A0
READ A0
qmD
D
DATA MASK (UPPER BYTE)
IN
) after one of the
A1
qmD
later. This
D
IN
DATA MASK (LOWER BYTE)
t
QMD=2
D
D
A
OUT
OUT
A0
A0
D
IN
must be executed within the ACT to PRE command
period (t
After the period (t
stop following the execution of the burst stop command
has elapsed, the write cycle terminates. This period
(t
latency.
output control operates independently on a byte basis
with the UDQM pin controlling upper byte output (pins
DQ8-DQ15) and the LDQM pin controlling lower byte
output (pins DQ0 to DQ7).
Since the U/LDQM pins control the device output buffers
only, the read cycle continues internally and, in particular,
incrementing of the internal burst counter continues.
A1
D
wbD
OUT
Integrated Silicon Solution, Inc. — www.issi.com
HI-Z
) is zero clock cycles, regardless of the CAS
A1
D
ras
IN
D
A2
OUT
max.) following the burst stop command.
HI-Z
BURST STOP
A2
wbD
BST
INVALID DATA
D
) required for burst data input to
t
WBD=0
OUT
A3
PRECHARGE (BANK 0)
PRE 0
HI-Z
t
RP
Don't Care
05/18/2010
Rev. E