IS42S16100E-6BLI-TR ISSI, IS42S16100E-6BLI-TR Datasheet - Page 30

• Manufacturer Part Number: IS42S16100E-6BLI-TR
• Description: DRAM 16M 1Mx16 166Mhz SDRAM, 3.3v
• Manufacturer: ISSI

Specifications of IS42S16100E-6BLI-TR

• Rohs: yes
• Data Bus Width: 16 bit
• Organization: 1 Mbit x 16
• Package / Case: BGA-60
• Memory Size: 16 Mbit
• Maximum Clock Frequency: 166 MHz
• Access Time: 6 ns
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 3 V
• Maximum Operating Current: 180 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 1000

30
IS42S16100E, IS45S16100E
Interval Between Read Command
A new command can be executed while a read cycle is
in progress, i.e., before that cycle completes. When the
second read command is executed, after the CAS latency
has elapsed, data corresponding to the new read command
is output in place of the data due to the previous read
command.
Interval Between Write Command
A new command can be executed while a write cycle is in
progress, i.e., before that cycle completes. At the point the
second write command is executed, data corresponding
to the new write command can be input in place of the
data for the previous write command.
CAS latency = 2, burstlength = 4
CAS latency = 3, burstlength = 4
COMMAND
COMMAND
CLK
DQ
CLK
DQ
READ (CA=A, BANK 0) READ (CA=B, BANK 0)
WRITE (CA=A, BANK 0) WRITE (CA=B, BANK 0)
READ A0
WRITE A0 WRITE B0
D
IN
A0
READ B0
t
CCD
D
IN
t
CCD
B0
D
OUT
D
A0
IN
B1
D
OUT
The interval between two write commands (t
at least one clock cycle.
The selected bank must be set to the active state before
executing this command.
The interval between two read command (t
at least one clock cycle.
The selected bank must be set to the active state before
executing this command.
D
B0
IN
Integrated Silicon Solution, Inc. — www.issi.com
B2
D
OUT
D
B1
IN
B3
D
OUT
B2
D
OUT
B3
ccD
ccD
) must be
) must be
05/18/2010
Rev. E