MT41J64M16JT-15E AIT:G Micron, MT41J64M16JT-15E AIT:G Datasheet - Page 95

• Manufacturer Part Number: MT41J64M16JT-15E AIT:G
• Description: DRAM Chip DDR3 SDRAM 1G-Bit 64Mx16 1.5V 96-Pin FBGA
• Manufacturer: Micron

Data Setup, Hold, and Derating
Table 59: Data Setup and Hold Values at 1 V/ns (DQS, DQS# at 2 V/ns) – AC/DC-Based
PDF: 09005aef84491df3
1Gb_AIT_AAT_DDR3_SDRAM.pdf – Rev. C 8/11 EN
t
t
t
t
DH (base) DC100
DS (base) AC175
DS (base) AC150
DS (base) AC135
Symbol
DDR3-800
125
150
75
–
The total
sheet
ble 51 (page 68)) to the
spectively. Example:
input signal has to remain above/below V
(page 97)).
Although the total setup time for slow slew rates might be negative (for example, a valid
input signal will not have reached V
tion), a valid input signal is still required to complete the transition and to reach
V
derating values may obtained by linear interpolation.
Setup (
last crossing of V
rate for a falling signal is defined as the slew rate between the last crossing of V
and the first crossing of V
slew rate line between the shaded V
derating value (see Figure 33 (page 98)). If the actual signal is later than the nominal
slew rate line anywhere between the shaded V
tangent line to the actual signal from the AC level to the DC level is used for derating
value (see Figure 35 (page 100)).
Hold (
last crossing of V
rate for a falling signal is defined as the slew rate between the last crossing of V
and the first crossing of V
slew rate line between the shaded DC-to-V
derating value (see Figure 34 (page 99)). If the actual signal is earlier than the nominal
slew rate line anywhere between the shaded DC-to-V
tangent line to the actual signal from the DC-to-V
ue (see Figure 36 (page 101)).
IH
/V
DDR3-1066 DDR3-1333
IL(AC)
t
t
DS (base) and
DH) nominal slew rate for a rising signal is defined as the slew rate between the
t
DS) nominal slew rate for a rising signal is defined as the slew rate between the
100
25
75
t
–
DS (setup time) and
. For slew rates that fall between the values listed in Table 61 (page 96), the
REF(DC)
IL(DC)max
t
t
DS (total setup time) =
DH (base) values (see Table 59 (page 95); values come from Ta-
30
65
–
–
and the first crossing of V
t
DS and
IL(AC)max
REF(DC)
and the first crossing of V
95
t
DDR3-1600
DH (hold time) required is calculated by adding the data
. If the actual signal is always later than the nominal
. If the actual signal is always earlier than the nominal
1Gb: x8, x16 Automotive DDR3 SDRAM
t
DH derating values (see Table 60 (page 96)), re-
10
45
IH(AC)
REF(DC)
–
–
Micron Technology, Inc. reserves the right to change products or specifications without notice.
/V
IH(AC)
-to-AC region, use the nominal slew rate for
REF(DC)
IL(AC)
t
Data Setup, Hold, and Derating
DS (base) +
DDR3-1866
REF(DC)
/V
) at the time of the rising clock transi-
IL(AC)
IH(AC)min
REF(DC)
region, use the nominal slew rate for
20
0
–
–
REF(DC)
-to-AC region, the slew rate of a
REF(DC)
for some time
region is used for derating val-
. Setup (
. Hold (
t
DS. For a valid transition, the
region, the slew rate of a
Unit
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ps
ps
ps
ps
t
DH) nominal slew
t
DS) nominal slew
t
VAC (see Table 63
V
V
V
V
Reference
IH(AC)
IH(AC)
IH(AC)
IH(DC)
/V
/V
/V
/V
REF(DC)
IH(DC)min
IL(AC)
IL(AC)
IL(AC)
IL(DC)