MT41J64M16JT-15E AIT:G Micron, MT41J64M16JT-15E AIT:G Datasheet - Page 189

• Manufacturer Part Number: MT41J64M16JT-15E AIT:G
• Description: DRAM Chip DDR3 SDRAM 1G-Bit 64Mx16 1.5V 96-Pin FBGA
• Manufacturer: Micron

Figure 111: Synchronous ODT (BC4)
Command
ODT
CK#
CKE
R
CK
TT
NOP
T0
NOP
T1
Notes:
NOP
T2
ODTH4
ODTLon = WL - 2
1. WL = 7. R
2. ODT must be held HIGH for at least ODTH4 after assertion (T1).
3. ODT must be kept HIGH ODTH4 (BC4) or ODTH8 (BL8) after the WRITE command (T7).
4. ODTH is measured from ODT first registered HIGH to ODT first registered LOW or from the registration of the
5. Although ODTH4 is satisfied from ODT registered HIGH at T6, ODT must not go LOW before T11 as ODTH4 must
NOP
T3
WRITE command with ODT HIGH to ODT registered LOW.
also be satisfied from the registration of the WRITE command at T7.
NOP
T4
TT,nom
NOP
T5
is enabled. R
NOP
T6
t
AON (MIN)
t
AON (MAX)
WRS4
ODTLoff = WL - 2
T7
TT(WR)
ODTH4 (MIN)
NOP
ODTLon = WL - 2
is disabled.
T8
R
TT,nom
ODTH4
NOP
T9
t
AOF (MIN)
NOP
T10
t
AOF (MAX)
NOP
T11
t
AON (MIN)
t
AON (MAX)
NOP
T12
ODTLoff = WL - 2
NOP
T13
R
TT,nom
NOP
T14
NOP
T15
Transitioning
NOP
T16
t
Don’t Care
AOF (MIN)
t
AOF (MAX)
NOP
T17