MT41J64M16JT-15E AIT:G Micron, MT41J64M16JT-15E AIT:G Datasheet - Page 160

• Manufacturer Part Number: MT41J64M16JT-15E AIT:G
• Description: DRAM Chip DDR3 SDRAM 1G-Bit 64Mx16 1.5V 96-Pin FBGA
• Manufacturer: Micron

Figure 83: Nonconsecutive WRITE to WRITE
DQS, DQS#
Figure 84: WRITE (BL8) to READ (BL8)
Command
DQS, DQS#
Command
Address
Address
CK#
DM
DQ
CK
DQ
CK#
CK
1
3
4
WRITE
Valid
T0
WRITE
Valid
T0
NOP
T1
NOP
Notes:
Notes:
T1
NOP
T2
1. DI n (or b) = data-in for column n (or column b).
2. Seven subsequent elements of data-in are applied in the programmed order following DO n.
3. Each WRITE command may be to any bank.
4. Shown for WL = 7 (CWL = 7, AL = 0).
1. NOP commands are shown for ease of illustration; other commands may be valid at these times.
2.
3. The BL8 setting is activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and MR0[12] = 1 during the WRITE command
4. DI n = data-in for column n.
5. RL = 5 (AL = 0, CL = 5), WL = 5 (AL = 0, CWL = 5).
NOP
WL = CWL + AL = 7
T2
T3
NOP
t
write data shown at T9.
at T0. The READ command at Ta0 can be either BC4 or BL8, depending on MR0[1:0] and the A12 status at Ta0.
WTR controls the WRITE-to-READ delay to the same device and starts with the first rising clock edge after the last
WL = 5
NOP
T4
NOP
T3
WRITE
Valid
T5
NOP
T4
T6
NOP
t
WPRE
NOP
NOP
T5
T7
DI
n
DI
n
n + 1
DI
n + 1
DI
WL = CWL + AL = 7
n + 2
T8
NOP
DI
n + 2
NOP
T6
DI
n + 3
DI
NOP
n + 4
n + 3
T9
DI
DI
n + 5
DI
NOP
n + 4
T7
DI
T10
n + 6
NOP
DI
n + 5
DI
n + 7
DI
NOP
T11
n + 6
NOP
T8
DI
n + 7
DI
T12
NOP
t
WPST
DI
b
NOP
T9
b + 1
DI
Indicates break
in time scale
T13
NOP
b + 2
DI
b + 3
DI
NOP
T10
NOP
T14
b + 4
DI
t
WTR
Transitioning Data
b + 5
DI
2
NOP
T15
b + 6
DI
NOP
T11
Transitioning Data
b + 7
DI
NOP
T16
READ
Ta0
Valid
Don’t Care
Don't Care
NOP
T17