MT41J64M16JT-15E AIT:G Micron, MT41J64M16JT-15E AIT:G Datasheet - Page 154

• Manufacturer Part Number: MT41J64M16JT-15E AIT:G
• Description: DRAM Chip DDR3 SDRAM 1G-Bit 64Mx16 1.5V 96-Pin FBGA
• Manufacturer: Micron

Figure 75: Method for Calculating
Figure 76:
PDF: 09005aef84491df3
1Gb_AIT_AAT_DDR3_SDRAM.pdf – Rev. C 8/11 EN
t
HZDQS,
t
RPRE Timing
t
HZDQS,
t
HZDQ
Notes:
t
HZDQ end point = 2 × T1 - T2
CK#
Single-ended signal provided
as background information
Single-ended signal provided
as background information
Resulting differential
signal relevant for
t
DQS#
CK
RPRE specification
DQS
1. Within a burst, the rising strobe edge is not necessarily fixed at
2. The DQS HIGH pulse width is defined by
3. The minimum pulse width of the READ preamble is defined by
DQS - DQS#
(MAX). Instead, the rising strobe edge can vary between
(MAX).
by
strobe case), and
strobe case); however, they tend to track one another.
mum pulse width of the READ postamble is defined by
t
QSL. Likewise,
T1
t
RPRE begins
T2
t
LZ and
T1
t
C
t
A
V
V
V
V
t
t
OH
OH
OL
OL
LZDQS (MAX) and
t
HZ
LZDQS (MIN) and
+ 2xmV
+ xmV
- xmV
- 2xmV
154
t RPRE
1Gb: x8, x16 Automotive DDR3 SDRAM
V
V
V
TT
V
Micron Technology, Inc. reserves the right to change products or specifications without notice.
TT
t
t
TT
HZDQS (MIN) are not tied to
HZDQS (MAX) are not tied to
TT
+ 2xmV
- 2xmV
+ xmV
- xmV
t
QSH, and the DQS LOW pulse width is defined
t
LZDQS,
t
B
t
RPRE ends
t
LZDQ begin point = 2 × T1 - T2
T2
t
T1
D
T2
t
RPST (MIN).
t
DQSCK (MIN) and
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t
LZDQS,
t
t
RPRE (MIN). The mini-
DQSCK (MIN) or
V
V
V
READ Operation
0V
TT
TT
TT
t
DQSCK (MIN) (early
t
DQSCK (MAX) (late
t
LZDQ
t
DQSCK
t
DQSCK