ATTINY26L8SU SL383 Atmel, ATTINY26L8SU SL383 Datasheet - Page 92

• Manufacturer Part Number: ATTINY26L8SU SL383
• Description: MCU 8-Bit ATtiny AVR RISC 2KB Flash 3.3V/5V 20-Pin SOIC T/R
• Manufacturer: Atmel

Start Condition Detector
Alternative USI Usage
Half-duplex Asynchronous
Data Transfer
4-bit Counter
12-bit Timer/Counter
Edge Triggered External
Interrupt
Software Interrupt
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ATtiny26(L)
The start condition detector is shown in Figure 49. The SDA line is delayed (in the range
of 50 to 300 ns) to ensure valid sampling of the SCL line. The start condition detector is
only enabled in Two-wire mode.
When Two-wire mode is selected, the USISIF flag is set (to one) when a start condition
is detected. When output disable mode or Three-wire mode is selected and (USICSx =
0b11 & USICLK = 0) or (USICS = 0b10 & USICLK = 0), any edge on the SCK pin sets
the flag.
The start condition detector is working asynchronously and can therefore wake up the
processor from the Power-down sleep mode. However, the protocol used might have
restrictions on the SCL hold time. Therefore, when using this feature in this case the
oscillator start-up time set by the CKSEL Fuses (see “Clock Systems and their Distribu-
tion” on page 24) must also be taken into the consideration. Refer to the description of
“Bit 7 – USISIF: Start Condition Interrupt Flag” on page 83 for further details.
When the USI unit is not used for serial communication, it can be set up to do alternative
tasks due to its flexible design.
By utilizing the Shift Register in Three-wire mode, it is possible to implement a more
compact and higher performance UART than by software only.
The 4-bit counter can be used as a stand-alone counter with overflow interrupt. Note
that if the counter is clocked externally, both clock edges will generate an increment.
Combining the USI 4-bit counter and Timer/Counter0 allows them to be used as a 12-bit
counter.
By setting the counter to maximum value (F) it can function as an additional external
interrupt. The overflow flag and interrupt enable bit are then used for the external inter-
rupt. This feature is selected by the USICS1 bit.
The counter overflow interrupt can be used as a software interrupt triggered by a clock
strobe.
1477J–AVR–06/07