ATTINY26L8SU SL383 Atmel, ATTINY26L8SU SL383 Datasheet - Page 48

• Manufacturer Part Number: ATTINY26L8SU SL383
• Description: MCU 8-Bit ATtiny AVR RISC 2KB Flash 3.3V/5V 20-Pin SOIC T/R
• Manufacturer: Atmel

Unconnected Pins
Alternate Port Functions
48
ATtiny26(L)
If some pins are unused, it is recommended to ensure that these pins have a defined
level. Even though most of the digital inputs are disabled in the deep sleep modes as
described above, floating inputs should be avoided to reduce current consumption in all
other modes where the digital inputs are enabled (Reset, Active mode, and Idle mode).
The simplest method to ensure a defined level of an unused pin, is to enable the internal
pullup. In this case, the pullup will be disabled during reset. If low power consumption
during reset is important, it is recommended to use an external pullup or pulldown. Con-
necting unused pins directly to V
excessive currents if the pin is accidentally configured as an output.
Most port pins have alternate functions in addition to being general digital I/Os. Figure
35 shows how the port pin control signals from the simplified Figure 32 can be overrid-
den by alternate functions. The overriding signals may not be present in all port pins, but
the figure serves as a generic description applicable to all port pins in the AVR micro-
controller family.
Figure 35. Alternate Port Functions
Note:
PUOExn:
PUOVxn:
DDOExn:
DDOVxn:
PVOExn:
PVOVxn:
DIEOExn: Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE
DIEOVxn: Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE
SLEEP:
Pxn
1. WPx, WDx, RLx, RPx, and RDx are common to all pins within the same port. clk
SLEEP, and PUD are common to all ports. All other signals are unique for each pin.
Pxn PULL-UP OVERRIDE ENABLE
Pxn PULL-UP OVERRIDE VALUE
Pxn DATA DIRECTION OVERRIDE ENABLE
Pxn DATA DIRECTION OVERRIDE VALUE
Pxn PORT VALUE OVERRIDE ENABLE
Pxn PORT VALUE OVERRIDE VALUE
SLEEP CONTROL
1
0
1
0
1
0
1
0
CC
or GND is not recommended, since this may cause
(1)
PUOExn
PUOVxn
PVOExn
PVOVxn
DIEOExn
DIEOVxn
SLEEP
DDOExn
DDOVxn
PUD:
WDx:
RDx:
RRx:
WPx:
RPx:
clk
DIxn:
AIOxn:
SYNCHRONIZER
D
L
I/O
SET
CLR
:
Q
Q
PULLUP DISABLE
WRITE DDRx
READ DDRx
READ PORTx REGISTER
WRITE PORTx
READ PORTx PIN
I/O CLOCK
D
DIGITAL INPUT PIN n ON PORTx
ANALOG INPUT/OUTPUT PIN n ON PORTx
PINxn
CLR
Q
Q
RESET
RESET
PORTxn
Q
Q
Q
Q
DDxn
CLR
CLR
D
D
clk
PUD
WDx
RDx
WPx
RRx
DIxn
AIOxn
RPx
I/O
1477J–AVR–06/07
I/O
,