ATTINY26L8SU SL383 Atmel, ATTINY26L8SU SL383 Datasheet - Page 77

• Manufacturer Part Number: ATTINY26L8SU SL383
• Description: MCU 8-Bit ATtiny AVR RISC 2KB Flash 3.3V/5V 20-Pin SOIC T/R
• Manufacturer: Atmel

1477J–AVR–06/07
Table 35. Compare Mode Select in PWM Mode
Note that in PWM mode, writing to the Output Compare Registers OCR1A or OCR1B,
the data value is first transferred to a temporary location. The value is latched into
OCR1A or OCR1B when the Timer/Counter reaches OCR1C. This prevents the occur-
rence of odd-length PWM pulses (glitches) in the event of an unsynchronized OCR1A or
OCR1B. See Figure 42 for an example.
Figure 42. Effects of Unsynchronized OCR Latching
During the time between the write and the latch operation, a read from OCR1A or
OCR1B will read the contents of the temporary location. This means that the most
recently written value always will read out of OCR1A or OCR1B.
When OCR1A or OCR1B contain $00 or the top value, as specified in OCR1C Register,
the output PB1(OC1A) or PB3(OC1B) is held low or high according to the settings of
COM1A1/COM1A0. This is shown in Table 36.
COM1x1
0
0
1
1
Unsynchronized OC1x Latch
Synchronized OC1x Latch
COM1x0
0
1
0
1
OC1x not connected.
OC1x not connected.
OC1x cleared on compare match. Set when TCNT1 = $01.
OC1x set one prescaled cycle after compare match. Cleared when
TCNT1 = $00.
OC1x cleared on compare match. Set when TCNT1 = $01.
OC1x not connected.
OC1x set one prescaled cycle after compare match. Cleared when
TCNT = $00
OC1x not connected.
Effect on Output Compare Pins
Glitch
Compare Value changes
Compare Value Changes
ATtiny26(L)
Counter Value
Compare Value
PWM Output OC1x
Counter Value
Compare Value
PWM Output OC1x
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