ATTINY26L8SU SL383 Atmel, ATTINY26L8SU SL383 Datasheet - Page 106

• Manufacturer Part Number: ATTINY26L8SU SL383
• Description: MCU 8-Bit ATtiny AVR RISC 2KB Flash 3.3V/5V 20-Pin SOIC T/R
• Manufacturer: Atmel

ADC Data Register – ADCL
and ADCH
ADLAR = 0
ADLAR = 1
106
ATtiny26(L)
• Bits 2..0 – ADPS2..0: ADC Prescaler Select Bits
These bits determine the division factor between the CK frequency and the input clock
to the ADC.
Table 47. ADC Prescaler Selections
When an ADC conversion is complete, the result is found in these two registers. The
ADLAR bit in ADMUX affect the way the result is read from the registers. If ADLAR is
set, the result is left adjusted. If ADLAR is cleared (default), the result is right adjusted. If
the result is left adjusted and no more than 8-bit precision is required, it is sufficient to
read ADCH. Otherwise, ADCL must be read first, then ADCH.
• ADC9..0: ADC Conversion Result
These bits represent the result from the conversion. For differential channels, this is the
absolute value after gain adjustment, as indicated in Table 46 on page 104. For single
ended channels, $000 represents analog ground, and $3FF represents the selected ref-
erence voltage minus one LSB.
Bit
$05 ($25)
$04 ($24)
Read/Write
Initial Value
Bit
$05 ($25)
$04 ($24)
Read/Write
Initial Value
ADPS2
0
0
0
0
1
1
1
1
ADC7
ADC9
ADC1
15
15
R
R
R
R
–
7
0
0
7
0
0
ADC6
ADC8
ADC0
14
14
R
R
R
R
–
6
0
0
6
0
0
ADPS1
0
0
1
1
0
0
1
1
ADC5
ADC7
13
13
R
R
R
R
–
5
0
0
–
5
0
0
ADC4
ADC6
12
12
R
R
R
R
–
4
0
0
–
4
0
0
ADPS0
0
1
0
1
0
1
0
1
ADC3
ADC5
11
11
–
3
R
R
0
0
–
3
R
R
0
0
ADC2
ADC4
10
10
R
R
R
R
–
2
0
0
–
2
0
0
ADC9
ADC1
ADC3
Division Factor
9
1
R
R
0
0
9
–
1
R
R
0
0
128
16
32
64
2
2
4
8
ADC8
ADC0
ADC2
R
R
R
R
8
0
0
0
8
–
0
0
0
1477J–AVR–06/07
ADCH
ADCH
ADCL
ADCL