ATTINY26L8SU SL383 Atmel, ATTINY26L8SU SL383 Datasheet - Page 82

• Manufacturer Part Number: ATTINY26L8SU SL383
• Description: MCU 8-Bit ATtiny AVR RISC 2KB Flash 3.3V/5V 20-Pin SOIC T/R
• Manufacturer: Atmel

Universal Serial
Interface – USI
Overview
82
ATtiny26(L)
The Universal Serial Interface, or USI, provides the basic hardware resources needed
for serial communication. Combined with a minimum of control software, the USI allows
significantly higher transfer rates and uses less code space than solutions based on
software only. Interrupts are included to minimize the processor load. The main features
of the USI are:
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A simplified block diagram of the USI is shown on Figure 44.
Figure 44. Universal Serial Interface, Block Diagram
The 8-bit Shift Register is directly accessible via the data bus and contains the incoming
and outgoing data. The register has no buffering so the data must be read as quickly as
possible to ensure that no data is lost. The most significant bit is connected to one of two
output pins depending of the wire mode configuration. A transparent latch is inserted
between the serial register output and output pin, which delays the change of data out-
put to the opposite clock edge of the data input sampling. The serial input is always
sampled from the Data Input (DI) pin independent of the configuration.
The 4-bit counter can be both read and written via the data bus, and can generate an
overflow interrupt. Both the serial register and the counter are clocked simultaneously
by the same clock source. This allows the counter to count the number of bits received
or transmitted and generate an interrupt when the transfer is complete. Note that when
an external clock source is selected the counter counts both clock edges. In this case
the counter counts the number of edges, and not the number of bits. The clock can be
selected from three different sources: the SCK pin, Timer 0 overflow, or from software.
The Two-wire clock control unit can generate an interrupt when a start condition is
detected on the Two-wire bus. It can also generate wait states by holding the clock pin
low after a start condition is detected, or after the counter overflows.
Two-wire Synchronous Data Transfer (Master or Slave, f
Three-wire Synchronous Data Transfer (Master, f
Data Received Interrupt
Wakeup from Idle Mode
In Two-wire Mode: Wake-up from All Sleep Modes, Including Power-down Mode
Two-wire Start Condition Detector with Interrupt Capability
USIDR
USISR
USICR
2
4-bit Counter
3
2
1
0
3
2
1
0
D Q
LE
[1]
TIM0 OVF
0
1
SCKmax
= f
SCLmax
Two-wire Clock
Control Unit
CK
/2, Slave f
= f
CK
CLOCK
HOLD
/16)
SCKmax
PB1
PB0
PB2
1477J–AVR–06/07
DO
(Output only)
DI/SDA
(Input/Open Drain)
= f
SCK/SCL
(Input/Open Drain)
CK
/4)