ATTINY26L8SU SL383 Atmel, ATTINY26L8SU SL383 Datasheet - Page 88

• Manufacturer Part Number: ATTINY26L8SU SL383
• Description: MCU 8-Bit ATtiny AVR RISC 2KB Flash 3.3V/5V 20-Pin SOIC T/R
• Manufacturer: Atmel

SPI Master Operation
Example
88
ATtiny26(L)
shifted by one) at negative edges. External clock mode 1 (USICS0 = 1) uses the oppo-
site edges versus mode 0, i.e., samples data at negative and changes the output at
positive edges. The USI clock modes corresponds to the SPI data mode 0 and 1.
Referring to the timing diagram (Figure 46.), a bus transfer involves the following steps:
1. The slave device and master device sets up its data output and, depending on
2. The master generates a clock pulse by software toggling the SCK line twice (C
3. Step 2. is repeated eight times for a comlpete register (byte) transfer.
4. After eight clock pulses (i.e., 16 clock edges) the counter will overflow and indi-
The following code demonstrates how to use the USI module as a SPI master:
The code is size optimized using only 8 instructions (+ ret). The code example assumes
that the DO and SCK pins are enabled as output in the DDRB Register. The value
stored in register r16 prior to the function is called is transferred to the slave device, and
when the transfer is completed the data received from the slave is stored back into the
r16 register.
The second and third instructions clears the USI Counter Overflow Flag and the USI
counter value. The fourth and fifth instruction set Three-wire mode, positive edge Shift
Register clock, count at USITC strobe, and toggle SCK (PORTB2). The loop is repeated
16 times.
the protocol used, enables its output driver (mark A and B). The output is set up
by writing the data to be transmitted to the serial Data Register. Enabling of the
output is done by setting the corresponding bit in the port data direction register
(DDRB2). Note that point A and B does not have any specific order, but both
must be at least one half SCK cycle before point C where the data is sampled.
This must be done to ensure that the data setup requirement is satisfied. The 4-
bit counter is reset to zero.
and D). The bit value on the slave and master’s data input (DI) pin is sampled by
the USI on the first edge (C), and the data output is changed on the opposite
edge (D). The 4-bit counter will count both edges.
cate that the transfer is completed. The data bytes transferred must now be
processed before a new transfer can be initiated. The overflow interrupt will wake
up the processor if it is set to Idle mode. Depending of the protocol used the
slave device can now set its output to high impedance.
SPITransfer:
SPITransfer_loop:
out
ldi
out
ldi
out
sbis
rjmp
in
ret
USIDR,r16
r16,(1<<USIOIF)
USISR,r16
r16,(1<<USIWM0)+(1<<USICS1)+(1<<USICLK)+(1<<USITC)
USICR,r16
USISR,USIOIF
SPITransfer_loop
r16,USIDR
1477J–AVR–06/07