MN85571AC PANASONIC [Panasonic Semiconductor], MN85571AC Datasheet - Page 9

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MN85571AC

Manufacturer Part Number
MN85571AC
Description
Single-Chip Audio/Video MPEG2 Encoder
Manufacturer
PANASONIC [Panasonic Semiconductor]
Datasheet
Note) 1. The absolute maximum ratings are limit values for stresses applied to the chip so that the chip will not be destroyed.
Note) * 1: When TS output is used, the PCR counter SCLK and VCLK jitter must be held within ±30 ppm as stipulated by the ISO/
1. Absolute Maximum Ratings
2. Recommended Operating Conditions at VSS = 0 V, AVSS = 0 V
Supply voltage 1
Supply voltage 2
Supply voltage 3
Input voltage
Output voltage
Average output current
Power dissipation
Operating temperature
Storage temperature
Supply voltage 1
Supply voltage 2
Supply voltage 3
Ambient temperature
System clock frequency
Video data input clock
frequency
Code data output clock
frequency
DMA transfer clock frequency
PCM master clock frequency
Electrical Characteristics
2. All of the 3.3 V VDD pins, 1.8 V VDD pins, and VSS pins must be connected externally to the 3.3 V power supply, 1.8 V
3. Connect bypass capacitors (at least 0.1 F) between the 3.3 V VDD and VSS pins, between the 1.8 V VDD and VSS pins,
4. The power supply voltages must be applied in the following order: first apply the 3.3 V system level (3.3V-VDD, AVDD),
* 2: The value shown for RCLKI is the stipulated value for forward clock input standalone mode. The maximum value for
Operation is not guaranteed within these ranges.
power supply, and ground, respectively.
and between the AVDD and VSS pins.
and then apply the 1.8 V system level (1.8V-VDD).
When removing power from this IC, first remove the 1.8 V system level (1.8V-VDD) and then remove the 3.3 V system level
(3.3V-VDD, AVDD).
IEC 13818-1 standard.
reverse clock input standalone mode is 16 MHz.
* 2
Item
Item
3.3V-VDD
1.8V-VDD
3.3V-VDD
1.8V-VDD
DMACLK
Symbol
Symbol
RCLKI
AVDD
AVDD
VCLK
SCLK
PCKI
Topr
Tstg
VO
PD
IO
VI
T
a
3.3V-VDD
AVDD 3.0 V to 3.6 V
DUTY: 50% 10%
Jitter: 50 ppm
3.3V-VDD
DUTY: 50% 10%
Jitter: 50 ppm
3.3V-VDD 3.0 V to 3.6 V
DUTY: 50% 10%
3.3V-VDD 3.0 V to 3.6 V
DUTY: 50% 10%
3.3V-VDD 3.0 V to 3.6 V
DUTY: 50% 10%
SDD00023AEM
0.3 to 3.3 V-VDD
0.3 to 3.3 V-VDD
Conditions
3.0 V to 3.6 V
3.0 V to 3.6 V
2.3 (4 layers)
* 1
* 1
40 to 125
0.3 to 4.6
0.3 to 2.5
0.3 to 4.6
0 to 70
Rating
24
0.3 (Upper limit: 4.6)
0.3 (Upper limit: 4.6)
1.65
Min
3.0
3.0
0
1.80
Typ
3.3
3.3
MN85571AC
18.432
Max
1.95
27.0
27.0
33.0
33.0
3.6
3.6
70
Unit
mA
W
V
V
V
V
V
C
C
MHz
MHz
MHz
MHz
MHz
Unit
V
V
V
C
9

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