MN85571AC PANASONIC [Panasonic Semiconductor], MN85571AC Datasheet - Page 14

• Manufacturer Part Number: MN85571AC
• Description: Single-Chip Audio/Video MPEG2 Encoder
• Manufacturer: PANASONIC [Panasonic Semiconductor]

MN85571AC
14
4. Video data input interface
5. PCM data input (audio data input) interface
prior to this product.
ing it only supports 16-bit quantization.
output PCM master clock output signal, the bit clock signal, and the left/right channel discrimination clock signal for
the external A/D converter. These signals are output from the PCKO, BCKIO, and LRCKIO pins, respectively.
bit clock signal, and a left/right channel discrimination clock signal, respectively. (In this mode, the PCKO pin must
be left open (N.C.).)
Interfaces (continued)
The video data input to this product assumes that the input signal has been time base corrected (TBC) in the stage
This product also assumes that the PCM data input and the video data input are locked in the stage prior to this product.
The PCM data input interface is provided for input of the audio data (PCM coded data) to the audio encoding block.
This product performs encoding for audio data that is sampled at a sampling frequency of 48 kHz.
It uses either Dolby Digital or linear PCM as the encoding technique.
There are limitations on the PCM data input quantization word length depending on the encoding technique used.
For Dolby Digital processing, this product supports 16, 18, 20, and 24-bit quantizations. For linear PCM process-
This product supports 2-channel (left/right) audio, and data is 1-bit serial data transmitted MSB first.
This product supports the I2S, left justified, and right justified formats as input formats.
The PCM data input interface can be switched between two modes: master mode and slave mode.
In master mode, a PCM master clock signal (256 or 384 fs) is input to this product’s PCKI pin and used to create the
In slave mode, the PCKI, BCKIO, and LRCKIO pins are used to input a PCM master clock signal (256 or 384 fs),
All the PCM data input interface parameter settings are set from multiplexing block SRISC microcode.
Interface pin descriptions
Interface pin descriptions
VIN[7:0]
VCLK
BCKIO
LRCKIO
ADIN
PCKI
PCKO
Pin Name
Pin Name
I/O
I/O
I/O
I/O
O
I
I
I
I
Video data input
Video data must be input in synchronization with the
video data input clock (VCLK).
The format of the input video data must be ITU-R
Video data input clock input
Bit clock output
Left/right channel discrimination clock output
PCM data (audio data) input
PCM master clock input
PCM master clock output
BT.656 (level D1, 4:2:2).
Description
Description
SDD00023AEM