MN85571AC PANASONIC [Panasonic Semiconductor], MN85571AC Datasheet - Page 10

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MN85571AC

Manufacturer Part Number
MN85571AC
Description
Single-Chip Audio/Video MPEG2 Encoder
Manufacturer
PANASONIC [Panasonic Semiconductor]
Datasheet
MN85571AC
10
1. Host interface
Read cycle time
HA[3:0] setup time from the NHCS falling edge
HA[3:0] setup time from the NHRE falling edge
HD[15:0] bus drive start time from the NHCS falling edge
HD[15:0] bus drive start time from the NHRE falling edge
HD[15:0] valid data output time from the NHCS falling edge
HD[15:0] valid data output time from the NHRE falling edge
HA[3:0] hold time from the NHCS rising edge
HA[3:0] hold time from the NHRE rising edge
HD[15:0] valid data hold time from the NHCS rising edge
HD[15:0] valid data hold time from the NHRE rising edge
1) Direct addressing access
2) Indirect addressing access
1) Direct addressing access
There are two techniques for accessing resources over the host interface as follows.
Interfaces
HA[3:0]
NHCS
NHRE
HD[15:0]
NHWE
Accesses to this product’s internal resources from an external host take place using the host interface block (HIF).
[Read]
Timing chart
AC Characteristics
"Hi-Z"
Item
t
t
adcs
adre
t
t
csgat
regat
t
csda
SDD00023AEM
t
reda
Valid Data
t
"H"
rcyc
Valid Data
Symbol Min
t
t
t
t
t
t
t
t
t
t
csdhd
t
csgat
regat
rcyc
adcs
adre
csda
reda
csad
read
dhd
t
csdhd
t
dhd
200
40
40
0
0
2
2
t
csad
t
read
Typ
Max
"Hi-Z"
135
135
2
2
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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