DM9161CI DAVICOM [Davicom Semiconductor, Inc.], DM9161CI Datasheet - Page 30

• Manufacturer Part Number: DM9161CI
• Description: Industrial-Temperature 10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
• Manufacturer: DAVICOM [Davicom Semiconductor, Inc.]

32
16.7
16.6
16.5
16.4
16.3
16.2
16.1
16.0
COLLED_CTL
RPDCTR-EN
SPLED_CTL
F_LINK_100
SMRST
MFPSC
RLOUT
SLEEP
0, RW
0, RW
0, RW
1, RW
0, RW
1, RW
0, RW
0, RW
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
latched into this bit at power-up/reset
1 = Enable Reduced MII
0 = Normal MII
Force Good Link in 100Mbps
1 = Force 100Mbps good link status
0 = Normal 100Mbps operation
This bit is useful for diagnostic purposes
Speed LED Disable
1 = Disable SPEED LED output.
0 = Normal SPEED LED output to indicate speed status
Collision LED Enable
1 = FDX/COL LED output is configured to indicate Full-
duplex/Collision status
0 = FDX/COL LED output is configured to indicate Full/half duplex
status
Reduced Power Down Control Enable
This bit is used to enable automatic reduced power down
1 = Enable automatic reduced power down
0 = Disable automatic reduced power down
Reset State Machine
When writes 1 to this bit, all state machines of PHY will be reset.
This bit is self-clear after reset is completed
MF Preamble Suppression Control
MII frame preamble suppression control bit
1 = MF preamble suppression bit on
0 = MF preamble suppression bit off
Sleep Mode
Writing a 1 to this bit will cause PHY entering the Sleep mode and
power down all circuit except oscillator and clock generator circuit.
When waking up from Sleep mode (write this bit to 0), the
configuration will go back to the state before sleep; but the state
machine will be reset
Remote Loop out Control
When this bit is set to 1, the received data will loop out to the
transmit channel. This is useful for bit error rate testing
Version: DM9161CI-DS-F01
DM9161CI
February 22, 2012
Final