DM9161CI DAVICOM [Davicom Semiconductor, Inc.], DM9161CI Datasheet - Page 23

• Manufacturer Part Number: DM9161CI
• Description: Industrial-Temperature 10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
• Manufacturer: DAVICOM [Davicom Semiconductor, Inc.]

AD
00 CONTROL
01
02
03
04 Auto-Neg.
05
06 Auto-Neg.
16 Specified
17 Specified
18
19
20
21
22
23 DIS_connec
24
25
26
29
30 MONITOR
8. MII Register Description
Key to Default
In the register description that follows, the default
column takes the form:
<Reset Value>, <Access Type> / <Attribute(s)>
Where ：
<Reset Value>:
25
D
Expansion
STATUS
Advertise
Link Part.
Conf/Stat
Conf/Stat
PWDOR
Specified
MDINTR
PHYID1
PHYID2
RCVER
RADVR
RSTLH
RLPAR
Config.
PSCR
Name
Ability
config
(PIN#)
10T
t
X
1
0
TSTSE1 TSTSE2 FORCE_
Reset
4B5B
Lh_led_
Page
Page
Rsvd
Cap.
Next
Next
FDX
Int_sts
100
mode
BP
T4
LP
15
0
0
0
1
Bit set to logic one
Bit set to logic zero
No default value
Value latched in from pin # at reset
FLP Rcv
TX FDX
Enable
Lh_mdint
Loop
back
Cap.
SCR
HDX
Reserve
100
Ack
Ack
BP
LP
LP
14
0
1
0
0
d
r
Reserved
TX HDX
Remote
Lh_cabst
ALIGN
Enable
Speed
Reserve
select
Fault
Cap.
FDX
HBE
TXSD
RF
BP
13
LP
10
1
1
0
1
d
s
BP_ADP
10 FDX
10 HDX Reserve
Reserved
FORCE_
Auto-N
Enable
Enable
Lh_isolat
SQUE
Reverse
Cap.
OK
12
FEF
0
1
1
1
Reserved
Reserved
d
e
Reversed
10 HDX
Repeater
Power
Down
preamble
Enable
PREAM
Fdx_ms
Cap.
Lh_rmii Lh_seril1
BLEX
JAB
11
0
1
0
1
d
k
x
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
Reserved
Reverse
Spd_msk Lnk_msk Int_msk Reserve
Isolate
TX10M_
amplitud
Adv
Serial
FC
FC
LP
PWR
10
10T
TX
0
0
0
d
0
e
Reserved
Restart
FEF_EN RMII_E
Auto-N
Reverse
NWAY_
Lh_repea
TX_PW
Adv
PWR
T4
LP
T4
9
0
0
d
Reserved
ter
R
0000
TX FDX
TX FDX
Receiver Error Counter
Duplex
Reserved MDIX_C
Lh_testm
PD10DR
Full
Adv
LP
8
1
1
N
ode
V
Reserved
Reserved
<Access Type>:
<Attribute (s)>:
Model No.
TX HDX
TX HDX
100LNK
001011
Force
Coll.
Test
Adv
Lh_op2
LP
PD100l
RO = Read only
RW = Read/Write
SC = Self clearing
P = Value permanently set
LL = Latching low
LH = Latching high
7
0
1
NTL
d
PHY ADDR [4:0]
TST_SE
10 FDX
10 FDX
Pream.
Supr.
Adv
AutoNeg
Reserve
LP
Lh_op1
L0
PDchip
_dlpbk
6
1
0
d
10 HDX
10 HDX
LEDCO
Compl.
Auto-N
L_SEL
Reserved
Adv
LP
Mdix_fix
Reverse
Lh_op0 Lh_phya
PDcrm
5
0
0
Value
d
RPDCTR
Remote
Pardet
Fault
Fault
Reserved
-EN
Disconnect_counter
Mdix_do
Fdx_chg Spd_chg Lnk_chg Reserve
PDaeq
4
0
0
wn
d4
Link Partner Protocol Selector Field
Advertised Protocol Selector Field
000_0000
LP Next
Pg Able
St. Mch
Reserved
Auto-N
Reset
Cap.
MonSel1 MonSel0 Rmii_acc
Lh_phya
Moni_en
PDdrv
3
1
0
d3
Version: DM9161CI-DS-F01
DM9161CI
Auto-N. Monitor Bit [3:0]
Version No.
Next Pg
Pream.
Status
Supr.
Lh_phya
Able
Link
0001
PDecli
2
0
0
d2
February 22, 2012
Moni_index
New Pg
Jabber
Detect
Sleep
mode
Lh_phya
PDeclo
Rcv
1
0
0
d1
u
d
LP AutoN
LoopOut
Remote
Reverse
PD_valu
Lh_phya
Polarity
Cap.
Cap.
Int_sts
Extd
PD10
0
1
0
d0
Final
e